XR16M570 Datasheet, PDF (35/52 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

XR16M570
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
4.10 Modem Status Register (MSR) - Write Only
This register provides the advanced features of XR16M570. Lower four bits of this register are reserved.
Writing to the higher four bits enables additional functions.
MSR[3:0]: Reserved
MSR[4]: Enable/Disable Transmitter (Requires EFR[4] = 1)
• Logic 0 = Enable Transmitter (default).
• Logic 1 = Disable Transmitter.
MSR[5]: Enable/Disable Receiver (Requires EFR[4] = 1)
• Logic 0 = Enable Receiver (default).
• Logic 1 = Disable Receiver.
MSR[6]: Enable/Disable 9-bit mode (Requires EFR[4] = 1)
For the 9-bit mode information, See ”Section 2.15, Normal Multidrop Mode” on page 18.
• Logic 0 = Normal 8-bit mode (default).
• Logic 1 = Enable 9-bit or Multidrop mode.
MSR[7]: Enable/Disable fast IR mode (Requires EFR[4] = 1)
The M570 supports the new fast IR transmission with data rate up to 1.152 Mbps.
• Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps (default).
• Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps. For more IR mode information, please
See ”Section 2.16, Infrared Mode” on page 19.
4.11 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12 Enhanced Mode Select Register (EMSR) - Write-only
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Level Count
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
TABLE 12: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0] _{Scratchpad is}
0
X
X
Scratchpad
1
X
0
RX FIFO Level Counter Mode
1
0
1
TX FIFO Level Counter Mode
1
1
1
Alternate RX/TX FIFO Counter Mode
During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been
asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO
Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and
so on and so forth.
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