XR16M570 Datasheet, PDF (16/52 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
REV. 1.0.0
2.10 Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 12):
• Enable auto RTS flow control using EFR bit-6.
• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.11 Auto RTS Hysteresis
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the selected RX
trigger level. The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches one trigger level
above the selected trigger level in the trigger table (Table 9). The RTS# pin will return LOW after the RX FIFO
is unloaded to one level below the selected trigger level. Under the above described conditions, the M570 will
continue to accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS#
output pin is asserted LOW (RTS On).
TABLE 4: AUTO RTS (HARDWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
RTS# DE-ASSERTED (HIGH)
(CHARACTERS IN RX FIFO)
RTS# ASSERTED (LOW)
(CHARACTERS IN RX FIFO)
1
1
4
0
4
4
8
1
8
8
14
4
14
14
14
8
2.12 Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 12):
• Enable auto CTS flow control using EFR bit-7.
If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an
interrupt when the CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend
16