XR16M654 Datasheet, PDF (58/58 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO

XR16M654/654D
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.0
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 29
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 30
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 30
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 30
TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 31
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 31
TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 32
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 33
TABLE 13: PARITY SELECTION ........................................................................................................................................................ 34
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 34
TABLE 14: INT OUTPUT MODES ..................................................................................................................................................... 35
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 36
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 37
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 37
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 38
TABLE 15: SAMPLING RATE SELECT ............................................................................................................................................... 38
4.12 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 38
TABLE 16: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 39
4.13 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE................... 40
4.14 FIFO STATUS REGISTER (FSTAT) - READ/WRITE...................................................................................... 40
TABLE 17: UART RESET CONDITIONS FOR CHANNELS A-D .................................................................................................. 41
ABSOLUTE MAXIMUM RATINGS.................................................................................. 42
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 42
ELECTRICAL CHARACTERISTICS ............................................................................... 42
DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 42
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 43
TA = -40O TO +85OC, VCC IS 1.62 TO 3.63V, 70 PF LOAD WHERE APPLICABLE ........................................... 43
FIGURE 15. CLOCK TIMING............................................................................................................................................................. 44
FIGURE 16. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 45
FIGURE 17. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D.................................................................................... 45
FIGURE 18. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D .................................................................................. 46
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 46
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 47
FIGURE 20. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 47
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 48
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 48
FIGURE 24. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 49
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D............................... 49
FIGURE 26. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D ............................... 50
PACKAGE DIMENSIONS ................................................................................................................................ 51
REVISION HISTORY...................................................................................................................................... 56
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