XR16M654 Datasheet, PDF (50/58 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO

XR16M654/654D
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.0
FIGURE 26. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D
Start
Bit
Stop
Bit
TX
(Unloading)
S D0:D7 T S D0:D7 T
IER[1]
enabled
ISR Read
D0:D7 S D0:D7 T
S D0:D7 T S D0:D7 T
T_SRT
T_SI
Last Data Byte
Transmitted
S D0:D7 T
ISR Read
INT*
TXRDY#
TX FIFO fills up
to trigger level
T_WRI
TX FIFO
Full
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
T_WT
IOW#
(Loading data
into FIFO)
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
TXDMA
50