XR16M654 Datasheet, PDF (57/58 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO

REV. 1.0.0
XR16M654/654D
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS .............................................................................................................................................. 1
FIGURE 1. XR16M654 BLOCK DIAGRAM .......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT FOR 100-PIN QFP PACKAGES IN 16 AND 68 MODE ....................................................................... 2
FIGURE 3. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES ......................... 3
FIGURE 4. PIN OUT ASSIGNMENT FOR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE............................................................... 4
PIN DESCRIPTIONS ........................................................................................................ 5
ORDERING INFORMATION ............................................................................................................................... 5
1.0 PRODUCT DESCRIPTION .................................................................................................................... 11
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 12
2.1 CPU INTERFACE .............................................................................................................................................. 12
FIGURE 5. XR16M654 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS .......................................................................... 12
2.2 DEVICE RESET ................................................................................................................................................. 13
2.3 CHANNEL SELECTION .................................................................................................................................... 13
TABLE 1: CHANNEL A-D SELECT IN 16 MODE ................................................................................................................................. 13
TABLE 2: CHANNEL A-D SELECT IN 68 MODE ................................................................................................................................. 13
2.4 CHANNELS A-D INTERNAL REGISTERS ....................................................................................................... 14
2.5 INT OUPUTS FOR CHANNELS A-D................................................................................................................. 14
TABLE 3: INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D ........................................................................................... 14
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D ................................................................................................. 14
2.6 DMA MODE ....................................................................................................................................................... 14
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D ........................................................... 15
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 15
FIGURE 6. TYPICAL CRYSTAL CONNECTIONS .................................................................................................................................. 15
2.8 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 15
FIGURE 7. BAUD RATE GENERATOR ............................................................................................................................................... 16
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 17
2.9 TRANSMITTER.................................................................................................................................................. 17
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 17
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 18
FIGURE 8. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 18
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 18
FIGURE 9. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 18
2.10 RECEIVER ....................................................................................................................................................... 19
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 19
FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................. 19
FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 20
2.11 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 20
2.12 AUTO RTS HYSTERESIS ............................................................................................................................... 20
TABLE 7: AUTO RTS (HARDWARE) FLOW CONTROL ........................................................................................................................ 20
2.13 AUTO CTS FLOW CONTROL......................................................................................................................... 21
FIGURE 12. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 21
2.14 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 22
TABLE 8: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 22
2.15 SPECIAL CHARACTER DETECT.................................................................................................................. 22
2.16 INFRARED MODE ........................................................................................................................................... 23
FIGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 23
2.17 SLEEP MODE WITH AUTO WAKE-UP .......................................................................................................... 24
2.18 INTERNAL LOOPBACK................................................................................................................................. 24
FIGURE 14. INTERNAL LOOP BACK IN CHANNELS A - D ................................................................................................................... 25
3.0 UART INTERNAL REGISTERS............................................................................................................. 26
TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 26
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ....................................... 27
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 28
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 28
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 28
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 28
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 28
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