XR21B1424_17 Datasheet, PDF (53/64 Pages) Exar Corporation – Enhanced 4-Ch Full-Speed USB UART

PIN_CFG_USB_STAT1 (0x01F) - Read/Write OTP
Controls the configuration of the USB_STAT1 pin during suspend state
Bit
7:5
4:2
1:0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
SEL
000: Assert logic ’1’ during SUSPEND or USB BUS_RESET else logic ’0’
001: Assert logic ’1’ during SUSPEND else logic ’0’
010: Assert logic ’1’ during LOW_PWR else logic ’0’
011: Assert logic ’1’ during USB BUS_RESET else logic ’0’
100: Assert logic ’1’ during SUSPEND or USB BUS_RESET else logic ’0’
101: Assert logic ’0’ during SUSPEND else logic ’1’
110: Assert logic ’0’ during LOW_PWR else logic ’1’
111: Assert logic ’0’ during USB BUS_RESET else logic ’1’
0
CTRL
00: Invalid, do not use
01: Output, open drain
10: Output, push-pull
11: Invalid, do not use
PIN_CFG_USB_STAT2 (0x020) - Read/Write OTP
Controls the configuration of the USB_STAT2 pin during suspend state
Bit
7:5
4:2
1:0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
SEL
000: Assert logic ’0’ during SUSPEND or USB BUS_RESET else logic ’1’
001: Assert logic ’1’ during SUSPEND else logic ’0’
010: Assert logic ’1’ during LOW_PWR else logic ’0’
011: Assert logic ’1’ during USB BUS_RESET else logic ’0’
100: Assert logic ’0’ during SUSPEND or USB BUS_RESET else logic ’1’
101: Assert logic ’0’ during SUSPEND else logic ’1’
110: Assert logic ’0’ during LOW_PWR else logic ’1’
111: Assert logic ’0’ during USB BUS_RESET else logic ’1’
0
CTRL
00: Invalid, do not use
01: Output, open drain
10: Output, push-pull
11: Invalid, do not use
XR21B1424
53 / 64
exar.com/XR21B1424
Rev 1C