XR21B1424_17 Datasheet, PDF (15/64 Pages) Exar Corporation – Enhanced 4-Ch Full-Speed USB UART

XR21B1424
7, 8, or 9 bit data
1^ST byte 7 6 5 4 3 2 1 0 _{7 = ‘0’ in 7 bit mode}
Figure 4: Receive Data Format
Normal receive operation with 9-bit data
The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun error or break
status information related to the data is discarded.
Wide mode receive operation with 5, 6, 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received data. The sec-
ond byte consists of the error bits and break status. Wide mode receive may be enabled by the RX_WIDE_MODE register.
Wide mode receive data format is shown in Figure 5.
5, 6, 7 or 8 bit mode
1^ST byte 7 6 5 4 3 2 1 0 5, 6, and 7 = ‘0’ in 5, 6, or 7 bit mode
2^ND byte x x x x O F B P
9 bit mode
P = Parity Error (=’0' if not enabled)
B = Break
F = Framing Error
O = Overrun Error
X = ‘0’
1^ST byte 7 6 5 4 3 2 1 0
2^ND byte x x x x O F B 8
B = Break
F = Framing Error
O = Overrun Error
X = ‘0’
Figure 5: Wide Mode Receive Data Format
Wide mode receive operation with 9-bit data
In 9 bit wide mode, the Parity bit is replaced by the 9th data bit. The framing and overrun errors and break condition remain
as shown in Figure 5.
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags are historical
flags indicating that an error has occurred since the previous request.
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Rev 1C