XR21B1424_17 Datasheet, PDF (14/64 Pages) Exar Corporation – Enhanced 4-Ch Full-Speed USB UART

XR21B1424
Reset
The XR21B1424 has three different types of resets: power-on reset or POR, hardware reset, and USB bus reset. The
results of each of the three types of resets are listed in Table 3.
Table 3: Device Resets
Reset Type
Device Actions
Power On Reset (POR)
Hardware Reset
USB Bus Reset
Resets all registers and pins to default states including any OTP modifications.
Locks OTP from further writes if Global Lock is set.
Resets all registers and pins to default states including any OTP modifications.
Locks OTP from further writes if Global Lock is set.
Resets USB Interface, re-enumerate device, reset all internal states, clear
UART FIFOs. Does not reset registers or pin configurations.
UART
The UART may be configured via USB control transfers from the USB host. The UART transmitter and receiver sections are
described separately in the following sections. At power-up, the XR21B1424 will default to 115.2 kbps, 8 data bits, no parity
bit, 1 stop bit, and no flow control. If a standard CDC driver accesses the XR21B1424, these defaults will be changed. See
“Device Driver” on page 11.
UART Wide mode allows for each character to be monitored for errors. Each received data character is accompanied by
another byte containing error status for parity, framing and overrun errors as well as break condition. In 9 bit Wide mode, the
9th bit may be used for denoting address or data in multidrop applications.
Transmitter
The transmitter consists of a 512-byte TX FIFO and a Transmit Shift Register (TSR). Once a Set transmit data interrupt out
or bulk-out packet has been received and the CRC has been validated, the data bytes in that packet are written into the TX
FIFO. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous data
byte. The TSR shifts the data out onto the TX output pin at the selected baud rate. The transmitter sends the start bit fol-
lowed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds the stop-bit(s). The transmit-
ter may be configured for 5, 6, 7 or 8 data bits with or without parity or 9 data bits without parity. If 5, 6, 7 or 8 bit data with
parity is selected, the TX FIFO contains 8 bits data and the parity bit is automatically generated and transmitted. If 9 bit data
is selected, parity cannot be generated. The 9th bit will not be transmitted unless the wide mode is enabled.
Wide Mode Transmit
When both 9 bit data and wide mode are enabled, two bytes of data will be written into the TX FIFO. The first byte is the first
8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte is bit-8 of the 9-bit data. The data that is transmitted on the TX
pin is as follows: start bit, 9-bit data, stop bit. Wide mode transmit may be enabled by the TX_WIDE_MODE register.
Receiver
The receiver consists of a 512-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the RSR via the
RX pin is transferred into the RX FIFO. Data from the RX FIFO is sent to the USB host by in response to a bulk-in request.
Depending on the mode, error / status information for that data character may or may not be stored in the RX FIFO with the
data.
Normal receive operation with 5, 6, 7 or 8-bit data
Received data is stored in the RX FIFO. Any parity, framing or overrun error or break status information related to the data
is discarded. The receive data format is shown in Figure 4.
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Rev 1C