XR21B1424_17 Datasheet, PDF (16/64 Pages) Exar Corporation – Enhanced 4-Ch Full-Speed USB UART

XR21B1424
RX FIFO Low Latency
In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to minimize host pro-
cessing. When there are 64 bytes of data in the RX FIFO, the XR21B1424 will acknowledge a bulk-in request from the host
and transfer the data packet. If there are less than 64 bytes in the RX FIFO, the XR21B1424 may respond to the bulk-in
request with a NAK indicating that data is not ready to transfer at that time. However, if there are less than 64 bytes in the
RX FIFO and no data has been received for more than 3 character times, the XR21B1424 will acknowledge the bulk-in
request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this behavior may increase latency unacceptably. The XR21B1424
has a low latency register bit that will enable the XR21B1424 to immediately transfer any received data in the RX FIFO to
the USB host without waiting for 3 character times. The custom driver may be used to automatically set the RX_FI-
FO_LOW_LATENCY register to enable low latency mode, or the user may manually set it. With the CDC-ACM driver, the
low latency mode is automatically set whenever the baud rate is set to a value of less than 40960 bps using the CDC_AC-
M_IF_SET_LINE_CODING command.
GPIO
Each UART has 10 GPIO pins in addition to the TX and RX pins. Each GPIO pin may also be configured for one or more
special functions. All GPIO pins as well as USB_STAT1 and USB_STAT2 may be configured for a variety of pin type options
using the GPIO_MODE register or by writing the OTP using XR_SET_OTP. All enabled pull-up and pull-down resistors are
maintained during the USB suspend state. Pin configurations set using XR_SET_OTP are enabled following the next
power-up reset and are permanent. During USB bus reset, resistors are disabled and are re-enabled after bus reset is de-
asserted. Pin configurations set using the GPIO_MODE register will be lost after POR or USB bus reset.
Programmable Output Clock
The GPIO6/CLK pin may be enabled as a clock output using the GPIO_MODE register. The OUTCLK register can be used
to program the output frequency of the clock from 24 MHz down to approximately 47 KHz. The duty cycle can also be pro-
grammed from 50/50 to a single low or high going pulse. The default values of zero for both DIV_HI and DIV_LO in the
OUTCLK register will result in a frequency of 24 MHz. For any non-zero values for DIV_HI and DIV_LO, the clock frequency
is determined by the formula:
FREQ = 24 MHz / (DIV_HI + DIV_LO). The duty cycle is determined by the ratio of DIV_HI to DIV_LO.
Flow Control
The XR21B1424 is able to perform both hardware and software flow control. Both hardware and software flow control
modes are configured via the GPIO_MODE and FLOW_CONTROL registers. In both modes, flow control is asserted when
the bytes in the RX FIFO reach the watermark set in the RX_THRESHOLD register.
Hardware flow control can either be RTS/CTS or DTR/DSR controlled. Note that although the default pin configuration for
GPIO5/RTS#/RS485 and GPIO4/CTS# are for RTS output and CTS input respectively, the hardware RTS/CTS flow control
mode must be set in the FLOW_CONTROL register in order to utilize the flow control functionality.
Automatic RTS/CTS Hardware Flow Control
Automatic RTS flow control is used to prevent data overrun errors in the local RX FIFO using the RTS signal to the remote
UART. The RTS signal will be asserted (low) when there are less than 450 bytes in the receive FIFO. When the RX FIFO
reaches the 450 byte threshold, the RTS pin will be de-asserted. The CTS# input is monitored by the remote UART to sus-
pend/restart the local transmitter. Refer to Figure 6. Conversely, when the remote UART reaches its receive FIFO threshold,
its RTS will be de-asserted, and the B1424 CTS input will cause the device to suspend data transmission.
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exar.com/XR21B1424
Rev 1C