XR21B1424_17 Datasheet, PDF (37/64 Pages) Exar Corporation – Enhanced 4-Ch Full-Speed USB UART

RX_FIFO_COUNT (0x044) - Read Only
This register is used to read the number of bytes currently in the receive FIFO.
Bit
15:10
9:0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
Count
Reports the number of bytes currently in the RX FIFO.
XR21B1424
RX_WIDE_MODE (0x045) - Read/Write
This register is used to enable the Wide Mode for the Receiver.
Bit
15:1
0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
EN
0: Normal (5, 6, 7, 8 or 9 bit data) mode
1: Wide mode. See “Wide Mode Transmit” on page 14, “Wide mode receive operation with 5, 6, 7 or 8-bit data” on page 15
and “Wide mode receive operation with 9-bit data” on page 15.
LOW_LATENCY (0x046) - Read/Write
This register is automatically set to logic ’1’ for baud rates below 40,960 bps when using the CDC-ACM driver. A custom
driver can also automatically enable low latency mode based upon the selected baud or the user may manually enable it by
writing to this register.
Bit
15:1
0
Default
Description
0
Reserved
These bits are reserved and should be written as ‘0’.
0
EN
0: Data from the RX FIFO is not immediately forwarded to the USB host following the bulk-in request until bMaxPacketSize
(normally 64 bytes) bytes have been received or a timeout period (of 3 character times) has been reached. (Note: When the
CDC-ACM driver is used, bMaxPacketSize is 63 bytes.)
1: Receive data is forwarded from RX FIFO immediately following the bulk-in request.
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Rev 1C