XR20M1280L32-0B Datasheet, PDF (53/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

REV. 1.0.0
XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 22. I²C-BUS TIMING DIAGRAM
Protocol
SCL
START
condition
(S)
Bit 7
MSB
(A7)
TSU;STA
TLOW THIGH
Bit 6
(A6)
1/F_SCL
T_F
TR
TBUF
SDA
THD;STA
TSU;DAT
THD;DAT
Bit 0
LSB
(R/W)
Acknowledge
(A)
STOP
condition
(P)
T_SP
TVD;DAT
TVD;ACK
TSU;STO
FIGURE 23. WRITE TO OUTPUT
SDA
GPIOn
SLAVE
ADDRESS
W A GPIOLVL REG. A
DATA
A
TD1
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