XR20M1280L32-0B Datasheet, PDF (4/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
PIN DESCRIPTIONS
REV. 1.0.0
Pin Description
NAME
QFN-24 QFN-32 QFN-40
TYPE
PIN#
PIN#
PIN#
DESCRIPTION
I2C (SPI) INTERFACE
I2C/SPI#
24
1
SDA
2
4
(GND)
SCL
3
5
IRQ#
4
6
A0
6
8
(CS#)
A1
5
7
(SI)
SO
1
3
(NC)
RESET#
7
9
1
I _I2_{C-bus or SPI interface select. I}2_{C-bus interface is selected if this}
pin is HIGH. SPI interface is selected if this pin is LOW
4
I/O _I2_{C-bus data input/output (open-drain). If SPI configuration is}
selected, then this pin should be tied LOW.
5
I _I2_{C-bus or SPI serial input clock.}
When the I²C-bus interface is selected, the serial clock idles HIGH.
When the SPI interface is selected, the serial clock idles LOW.
6
OD _{Interrupt output (open-drain, active LOW).}
8
I _I2_{C-bus device address select A0 or SPI chip select. If I}2_{C-bus con-}
figuration is selected, this pin along with the A1 pin allows user to
change the device’s base address. If SPI configuration is selected,
this pin is the SPI chip select pin (Schmitt-trigger, active LOW).
7
I _I2_{C-bus device address select A1 or SPI data input pin. If I}2_C-bus
configuration is selected, this pin along with A0 pin allows user to
change the device’s base address. If SPI configuration is selected,
this pin is the SPI data input pin.
3
O _{SPI data output pin. If I2C-bus configuration is selected, this pin}
must be left unconnected.
10
I _{Reset (active LOW) - A longer than 40 ns LOW pulse on this pin will}
reset the internal registers and all outputs. The UART transmitter
output will be idle and the receiver input will be ignored.
MODEM I/O and GPIOs
TX
13
28
RX
14
29
RTS#
15
27
CTS#
12
26
GPIO0/DTR# 20
25
GPIO1/DSR# 19
24
36
O _{UART Transmit Data or infrared encoder data. Standard transmit}
and receive interface is enabled when MCR[6] = 0. In this mode, the
TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
37
I _{UART Receive Data or infrared receive data. Normal receive data}
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
35
O _{UART Request-to-Send (active low) or general purpose output. This}
output must be asserted prior to using auto RTS flow control, see
EFR[6], MCR[1] and IER[6].
34
I _{UART Clear-to-Send (active low) or general purpose input. It can}
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
33
I/O _{General purpose I/O or UART Data-Terminal-Ready (active low).}
32
I/O _{General purpose I/O or UART Data-Set-Ready (active low).}
4