XR20M1280L32-0B Datasheet, PDF (35/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

REV. 1.0.0
XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
TABLE 13: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER FCTR FCTR FCR FCR FCR
TABLE BIT-5 BIT-4 BIT-7 BIT-6 BIT-5
FCR
RECEIVE
BIT-4 TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
Table-A 0
0
0
0
1 (default) 16C550, 16x255x,
0
0
0
1
1 (default)
4
16x554, 16x57x,
16x58x
1
0
8
1
1
14
Table-B 0
1
0
0
0
1
1
0
1
1
0
0
8
0
1
16
1
0
24
1
1
28
16
16C650A, 16L651,
8
16x265x, 16x564
24
30
Table-C 1
0
0
0
0
1
1
0
1
1
0
0
8
0
1
16
1
0
56
1
1
60
8
16x654
16
32
56
Table-D 1
1
X
X
X
X Programmable Programmable 16x275x, 16C285x,
via TRG
register.
via TRG
register.
16C850, 16C854,
16C864
FCTR[7] = 0. FCTR[7] = 1.
3.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
0
0
1
1
BIT-0
0
1
0
1
WORD LENGTH
5 (default)
6
7
8
35