XR20M1280L32-0B Datasheet, PDF (19/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

REV. 1.0.0
XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 16. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Shift Data Bit
Register (RSR)
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 17. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X or 8X or 4X Clock
( DLD[5:4] )
128 bytes by 11-bit wide
FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Receive
Data FIFO
Receive
Data
Data Bit
Validation
Receive Data Characters
Example
: - RX FIFO trigger level selected at 16 bytes
(See Note Below)
Data falls to
8
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
FIFO
Trigger=16
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to
56
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RXFIFO1
19