XR20M1280L32-0B Datasheet, PDF (29/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR20M1280
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
111
REG
NAME
EMSR
111
FC
0 0 0 DREV
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
WR
Xoff
LSR
Rsvd
interrupt interrupt
mode mode
select select
Modem
3-State
Control
Invert
RTS in
RS485
mode
RD Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
Baud Rate Generator Divisor
RD Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
000
001
DLL RD/WR Bit-7
DLM RD/WR Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
010
000
000
001
010
100
101
110
111
100
101
110
111
DLD
RD/WR
BRG
select
Enable 4X Mode 8X Mode
Indepen-
dent
BRG
Bit-3
Enhanced Registers
FC
RD Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
TRIG WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
FCTR RD/WR RX/TX
select
Swap
SPR
Trigger
Table
bit-1
Trigger
Table
bit-0
Auto
RS485
Half-
Duplex
EFR
RD/WR Auto
CTS#
Enable
Auto
RTS#
Enable
Special Enable
Char _{IER [7:4],}
Select _{ISR [5:4],}
FCR[5:3],
MCR[7:5],
DLD,
SHR,
SFR
Soft-
ware
Flow
Cntl
Bit-3
XON1 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
XON2 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
XOFF1 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
XOFF2 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
Bit-15/ Bit-14/ Bit-13/ Bit-12/
GPIOINT RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-11/
Bit-3
Bit-15/ Bit-14/ Bit-13/ Bit-12/
GPIO3T RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-11/
Bit-3
Bit-15/ Bit-14/ Bit-13/ Bit-12/
GPIOINV RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-11/
Bit-3
Bit-15/ Bit-14/ Bit-13/ Bit-12/
GPIOSEL RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-11/
Bit-3
BIT-2 BIT-1 BIT-0 COMMENT
Send
TX
imme-
diate
Bit-2
FIFO
count
control
bit-1
Bit-1
FIFO
count
control
bit-0
Bit-0
LCR≠0xBF
FCTR[6]=1
SFR[0]=0
Bit-2 Bit-1
Bit-2
Bit-2
Bit-1
Bit-1
Bit-2 Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
LCR[7] = 1
LCR≠0xBF
DLL= 0x00
DLM= 0x00
LCR[7] = 1
LCR≠0xBF
DLD[7:6]
LCR[7] = 1
LCR≠0xBF
EFR[4] = 1
Bit-2
Bit-2
invert
RX IR
Bit-1
Bit-1
Rsvd
Bit-0
Bit-0
PWRDN
#
control
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
Bit-2
Bit-2
Bit-2
Bit-2
Bit-10/
Bit-2
Bit-10/
Bit-2
Bit-10/
Bit-2
Bit-10/
Bit-2
Bit-1
Bit-1
Bit-1
Bit-1
Bit-9/
Bit-1
Bit-9/
Bit-1
Bit-9/
Bit-1
Bit-9/
Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
Bit-8/
Bit-0
Bit-8/
Bit-0
Bit-8/
Bit-0
Bit-8/
Bit-0
LCR=0XBF
SFR[0]=0
LCR=0XBF
SFR[0]=1
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