XR20M1280L32-0B Datasheet, PDF (1/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
MAY 2011
REV. 1.0.0
GENERAL DESCRIPTION
The XR20M1280¹ (M1280) is a single-channel I²C/
SPI Universal Asynchronous Receiver and
Transmitter (UART) with integrated level shifters and
128 bytes of transmit and receive FIFOs.
For flexibility in a mixed voltage environment, the
M1280 has 4 VCC pins. There is a VCC pin for the
core, a VCC pin for the UART signals, a VCC pin for
the CPU interface signals and a VCC pin for the
GPIO signals. The VCC pins for the UART, GPIO
and I²C/SPI interface signals allow for the M1280 to
interface with devices operating at different voltage
levels eliminating the need for external voltage level
shifters. The VCC pin for the core voltage helps
lower the overall power consumption of applications
that use slower data rates.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection and
Address Byte Control features increase the
performance by simplifying the software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. In addition, the Fractional
Baud Rate Generator feature provides flexibility for
crystal/clock frequencies for generating standard and
non-standard baud rates.
The M1280 has programmable transmit and receive
FIFO trigger levels, automatic hardware and software
flow control, and data rates of up to 24 Mbps. Power
consumption of the M1280 can be minimized by
enabling the sleep mode.
The M1280 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M1280 has a selectable
I²C/SPI bus interface.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
• Integrated Level Shifters on CPU interface, UART
and GPIO signals
• Selectable I²C/SPI bus interface
• 26MHz maximum SPI clock
• 24Mbps maximum UART data rate
• Up to 16 GPIOs
• 128-Bytes TX and RX FIFOs
• Programmable TX/RX trigger levels
• TX/RX FIFO Level Counters
• Independent TX/RX Baud Rate Generator
• Fractional Baud Rate Generator
• Auto RTS/CTS Hardware Flow Control
• Auto XON/XOFF Software Flow Control
• Auto RS-485 Half-Duplex Direction Control
• Multidrop mode w/ Auto Address Detect (RX)
• Multidrop mode w/ Address Byte Control (TX)
• Sleep Mode with Automatic Wake-up
• Infrared (IrDA 1.0 and 1.1) mode
• 1.62V to 3.63V supply operation
• 5V tolerant inputs
• Crystal oscillator or external clock input
APPLICATIONS
• Personal Digital Assistants (PDA)
• Cellular Phones/Data Devices
• Battery-Operated Devices
• Global Positioning System (GPS)
• Bluetooth
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com