XRT75VL00_08 Datasheet, PDF (46/50 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75VL00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.6
8.0 DIAGNOSTIC FEATURES:
8.1 PRBS Generator and Detector:
The XRT75VL00 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. This feature is only available in Host mode. With the PRBSEN bit = “1”, the transmitter will
send out PRBS of 2²³-1 in E3 rate or 2¹⁵-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is
also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go “Low” to
indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the PRBSLS bit will
be set to “1” and RNEG/LCV pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “1” to INSPRBS bit. The receiver at RNEG/LCV pin will pulse “High” for half RxClk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to
INSPRBS bit and followed by a “1”.
When PRBS mode is enabled, the PRBS counter starts counting each single bit error. The PRBS counter is 16
bits wide. The current value in the counter can be read via two readback operations of the Serial I/O registers.
1) Either the Least Significant Byte (LSB, address 0x30) or the Most Significant Byte (MSB, address 0x31) can
be read first. The value of the un-read register will be copied into the Holding register (address 0x38) and both
the LSB and MSB registers will be reset to zero.
2) Read the Holding register and concatenate the result with the value from the first read operation to get the
full 16 bit counter value.
When the PRBS mode is first enabled, errors will be counted while the receiver logic is synchronizing to the
PRBS pattern. When RNEG/LCV goes “Low” indicating PRBS synchronization, reset the counter by reading
either the LSB or the MSB register.
Figure 25 shows the status of RNEG/LCV pin when the XRT75VL00 is configured in PRBS mode.
FIGURE 25. PRBS MODE
RClk
RNEG/LCV
SYNC LOSS
PRBS SYNC
Single Bit Error
8.2 LOOPBACKS:
The XRT75VL00 offers three loopback modes for diagnostic purposes. In Hardware mode, the loopback
modes are selected via the RLB and LLB pins. In Host mode, the RLB and LLB bits in the control registers
select the loopback modes.
8.2.1 ANALOG LOOPBACK:
In this mode, the transmitter outputs (TTIP and TRING) are connected internally to the receiver inputs (RTIP
and RRING) as shown in Figure 26. Data and clock are output at RCLK, RPOS and RNEG pins for the
corresponding transceiver. Analog loopback exercises most of the functional blocks of the device including the
jitter attenuator which can be selected in either the transmit or receive path.
XRT75VL00 can be configured in Analog Loopback either in Hardware mode via the LLB and RLB pins or in
Host mode via LLB and RLB bits in the channel control registers.
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