XRT75VL00_08 Datasheet, PDF (41/50 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

REV. 1.0.6
XRT75VL00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x01 R/W
D0
DMOIE Writing a “1” to this bit field enables the DMO inter-
0
rupt and triggers an interrupt when the transmitter
driver fails. Writing a “0” disables the interrupt.
D1
RLOSIE Writing a “1” to this bit field enables the RLOS inter-
0
rupt and triggers an interrupt when the RLOS condi-
tion occurs. Writing a “0” disables the interrupt.
D2
RLOLIE Writing a “1” to this bit field enables the RLOL inter-
0
rupt and triggers an interrupt when RLOL condition
occurs. Writing a “0” disables the interrupt.
D3
FLIE
Writing a “1” to this bit field enables the FL interrupt
0
and triggers an interrupt when the FIFO Limit of the
Jitter Attenuator is within 2 bits of overflow/underflow
condition. Writing a “0” disables the interrupt.
NOTE: This bit field is ignored when the Jitter
Attenuator is disabled.
D4
PRBSIE Writing a “1” to this bit enables the PRBS bit error
0
interrupt.
D5
CNT_SATIE Writing a “1” to this bit enables the PRBS error-
0
counter saturation interrupt. When the PRBS error
counter reaches 0xFFFF, an interrupt will be gener-
ated.
0x02 Reset
D0
Upon
Read
DMOIS This bit is set to “1” every time a DMO status change
0
has occurred since the last cleared interrupt.This bit
is cleared when read.
D1
RLOSIS This bit is set to “1” every time a RLOS status change
0
has occurred since the last cleared interrupt. This bit
is cleared when read.
D2
RLOLIS This bit is set to “1” every time a RLOL status change
0
has occurred since the last cleared interrupt. This bit
is cleared when read.
D3
FLIS
This bit is set to “1” every time a FIFO Limit status
0
change has occurred since the last cleared interrupt.
This bit is cleared when read.
D4
PRBSIS This bit is set to “1” when a PRBS bit error is
0
detected. This bit is cleared when read.
D5
CNT_SATIS This bit is set to “1” when the PRBS error counter has
0
saturated (0xFFFF). This bit is cleared when read.
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