XRT75VL00_08 Datasheet, PDF (44/50 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75VL00
E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.6
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x07 R/W
D0
JA0
This bit along with JA1 bit configures the Jitter Attenu-
0
ator as shown in the table below.
0x08
JA0
JA1
Mode
0
0
16 bit FIFO
0
1
32 bit FIFO
1
0
Disable Jitter
Attenuator
1
1
Disable Jitter
Attenuator
D1
JATx/Rx Writing a “1” to this bit selects the Jitter Attenuator in
0
the Transmit Path. A “0” selects in the Receive Path.
D2
JA1
This bit along with the JA0 configures the Jitter Atten-
0
uator as shown in the table.
D3
PNTRST Setting this bit to “1” resets the Read and Write point-
0
ers of the jitter attenuator FIFO.
Reserved
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL
ADDRESS
(HEX)
0x20
TYPE
R/W
0x21
Read
Only
0x22 -
0x2F
0x30
0x31
0x32-
0x37
0x38
0x39-
0x3D
Reset
Upon
Read
Reset
Upon
Read
Read
Only
BIT
LOCATION
D0
D0
D[7:0]
D[7:0]
D[7:0]
SYMBOL
INTEN
INTST
DESCRIPTION
DEFAULT
VALUE(BIN)
Bit 0 = INTEN Writing a “1” to this bit enables the
0
interrupts.
Bit 0 = INTST bit is set to “1” if an interrupt service is
0
required. The source level interrupt status register is
read to determine the cause of interrupt.
Reserved
PRBSmsb PRBS error counter MSB [15:8]
PRBSlsb PRBS error counter LSB [7:0]
Reserved
PRBShold PRBS Holding Register
Reserved
42