XRT94L33_06 Datasheet, PDF (452/465 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET

XRT94L33
Rev.1.2.0.
xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
UTOPIA Interface block negates the RxUClav signal. The ATM Layer processor detects that the RxClav
signal has toggled “low”; at clock edge #2. Hence, the ATM Layer processor will finish reading in the current
ATM cell; from the Receive UTOPIA Interface block of the XRT94L33 (e.g., words W25 and W26).
Afterwards, the ATM Layer processor will negate the RxUEnB* signal and will cease to read in anymore ATM
cell data from the Receive UTOPIA Interface block; until RxUClav toggles “high” again.
The RxFIFO accumulates enough cell data to make up a complete ATM cell shortly before clock edge #5. At
this point the Receive UTOPIA Interface block reflects this fact by asserting the RxUClav signal. The ATM
Layer processor detects that the RxUClav signal has toggled “high” at clock edge #5. Consequently, the ATM
Layer processor then asserts the RxUEnB* signal (e.g., toggles it “low”) after clock edge #5. The Receive
UTOPIA Interface block detects the fact that the RxUEnB* input pin has been asserted at clock edge #6. The
Receive UTOPIA Interface block then responds to this signaling by placing the first word of the next cell on
the Receive UTOPIA Data bus. Afterwards, the ATM Layer processor continues to read in the remaining
words of this cell.
2.3.5.1.2.5 Multi-PHY Operation
The XRT94L33 permits the user to configure it to operate in the “Multi-PHY” Mode. This can be
accomplished by setting Bit 6 (Multi-PHY Mode), within the “Receive UTOPIA Control Register – Byte 0” to “1”
as depicted below.
Receive UTOPIA/POS-PHY Control Register – Byte 0 (Address = 0x0503)
BIT 7
UTOPIA
Level 3
Disable
R/W
1
BIT 6
Multi-PHY
Polling
Enable
R/W
1
BIT 5
Back to
Back Polling
Enable
R/W
0
BIT 4
Direct
Status
Indication
Enable
R/W
0
BIT 3
BIT 2
Receive UTOPIA/POS-PHY
Data Bus Width
R/W
R/W
1
1
BIT 1
BIT 0
Cell Size[1:0]
R/W
R/W
X
X
Note: This configuration setting does not apply to the Transmit UTOPIA Interface block. Therefore, the user will also
need to configure the Transmit UTOPIA Interface block into the “Multi-PHY” Mode, as described in Section _.
In the “Multi-PHY” operating mode, the ATM Layer Processor may be writing data into and reading data from
several UNI (e.g., PHY Layer) devices in parallel. Figure 114 presents an illustration of a simple “Multi-PHY
System” consisting of a single ATM Layer Processor being interfaced to two (2) UNI devices. When the
XRT94L33 is operating in the Multi-PHY mode, the Receive UTOPIA Interface block will support two kinds of
operations with the ATM Layer Processor.
• Polling for UNI (PHY Layer) devices that contain ATM cell waiting to be read.
• Selecting which UNI (out of several possible UNI devices) to read ATM cell data from.
Each of these operations is discussed in the sections below. However, prior to discussing each of these
operations, the reader must understand the following.
“Multi-PHY” operation involves the use of one (1) ATM Layer processor and several UNI (or PHY-Layer)
devices, within a system. The ATM Layer processor is expected to read/write ATM cell data from/to these
UNI devices. Hence, “Multi-PHY” operation requires, at a minimum, some means for the ATM Layer
processor to uniquely identify a particular UNI device (among all of the UNI devices within the “Multi-PHY”
system) that it wishes to “poll”, write ATM cell data to, or read ATM cell data from. Actually, “Multi-PHY”
operation provides an addressing scheme allows the ATM Layer processor to uniquely identify “UTOPIA
Interface Blocks” (e.g., Transmit and Receive) within all of the UNI devices, operating in the “Multi-PHY”
system. In order to uniquely identify a given “UTOPIA Interface block”, within a “Multi-PHY” system, each
“Transmit and Receive UTOPIA Interface Blocks are assigned a 5-bit “UTOPIA address” value. The user
assigns this address value to a particular “Receive UTOPIA Interface block” by writing this address value into
452