XRT94L33_06 Datasheet, PDF (171/465 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
XRT94L33
Rev.1.2.0.
Transmit UTOPIA Control Register – Byte 0, Address = 0x0483
BIT 7
UTOPIA
Level
BIT 6
Multi-PHY
Mode
BIT 5
Back-to-
Back Polling
Enable
BIT 4
Direct
Status
Access
BIT 3
BIT 2
Transmit UTOPIA
Data Bus Width[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
1
1
BIT 1
BIT 0
Cell_Size_Sel[1:0]
R/W
R/W
X
X
2.2.2 TRANSMIT ATM CELL PROCESSOR BLOCK
The next functional block, within the Transmit Path of the XRT94L33 is the Transmit ATM Cell Processor
Block. Figure 19 presents an illustration of the XRT94L33 Functional Block Diagram, with the “Transmit ATM
Cell Processor Block” highlighted.
Figure 19: Illustration of the XRT94L33 Functional Block Diagram, with the Transmit ATM Cell
Processor block highlighted
SSTTSS-3-3
PPEECCLL
IInnteterrfafaccee
BBlolocckk
SSTTSS-3-3
TTeeleleccoomm
BBuuss
IInnteterrfafaccee
BBlolocckk
SSTTSS-3-3
CCDDRR
BBlolocckk
TTrraannssmmitit
SSTTSS-3-3
TTOOHH
PPrroocceessssoorr
BBlolocckk
TTrraannssmmitit
SSTTSS-3-3cc
PPOOHH
PPrroocceessssoorr
BBlolocckk
RReecceeivivee
SSTTSS-3-3
TTOOHH
PPrroocceessssoorr
BBlolocckk
RReecceeivivee
SSTTSS-3-3cc
PPOOHH
PPrroocceessssoorr
BBlolocckk
XRT94L33 – Channel 0 _{MMicicrroopprroocceessssoorr}
IInnteterrfafaccee
BBlolocckk
CClolocckk
SSyynnththeessizizeerr
BBlolocckk
TTrraannssmmitit
AATTMM
CCeellllPPrroocceessssoorr
BBlolocckk
TTrraannssmmitit
PPPPPP
PPrroocceessssoorr
BBlolocckk
RReecceeivivee
AATTMM
CCeellllPPrroocceessssoorr
BBlolocckk
RReecceeivivee
PPPPPP
PPrroocceessssoorr
BBlolocckk
TTrraannssmmitit
UUTTOOPPIAIA
IInnteterrfafaccee
BBlolocckk
TTrraannssmmitit
PPOOSS-P-PHHYY
IInnteterrfafaccee
BBlolocckk
RReecceeivivee
UUTTOOPPIIAA/ _/
IInnteterrfafaccee
BBlolocckk
RReecceeivivee
PPOOSS-P-PHHYY
IInnteterrfafaccee
BBlolocckk
171