XRT94L33_06 Datasheet, PDF (156/465 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET

XRT94L33
Rev.1.2.0.
xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Table 12 The Relationship between the contents of Bits 1 and 0 (Cell_Size_Sel[1:0]) within the
Transmit UTOPIA Control Register, and the number of octets per cell that will be processed by the
Transmit UTOPIA Interface blocks per assertion of TxUSOC
CELL_SIZE_SEL[1:0]
00
NUMBER OF BYTES/CELLS
52 bytes/cell
01
53 bytes/cell (only valid if the Transmit UTOPIA Data Bus Width = 8 bits)
10
54 bytes/cell
11
Unused
Once the user has implemented his/her selection for the cell size, then the Transmit UTOPIA Interface block
will be configured to accept the “Cell Size” number of octets, per each assertion of the “TxUSoC” input pin.
Once the Transmit UTOPIA Interface block has accepted “Cell Size” number of bytes then it will not accept
any more octets until the “TxUSoC” input pin has been pulsed “high” again.
Note: In this case the Transmit UTOPIA Interface block will cease accepting more octets, even if the “TxUEnB* input
pin is pulled “low”. These additional bytes are simply ignored by the “Transmit UTOPIA Interface” block.
2.2.1.3.3 Cell-Level Handshaking
ATM Forum documentation refers to both “Cell Level” and “Octet-Level” handshaking. However, the
XRT94L33 only supports the “Cell-Level” Handshaking mode. Octet-level handshaking is NOT supported. In
the “Cell-Level” Handshaking mode, when the XRT94L33 sets the TxUClav output pin to a logic “1”, it means
that the Tx FIFO has enough remaining empty space for it to receive at least one more full cell of data from
the ATM Layer processor. However, when TxUClav toggles from “high” to “low”, it indicates that the very next
cell (following the one that is currently being written into the Transmit UTOPIA Interface block) cannot be
accepted by the Tx FIFO. Conversely, once the TxUClav output pin has returned to the logic “1” level, it
indicates that at least one more full cell may be written into the TxFIFO by the ATM Layer processor. The
ATM Layer processor is expected to poll the state of the TxUClav output pin towards the end of transmission
of the cell currently being written and to proceed with writing the next ATM cell into the Transmit UTOPIA
Interface block only if TxUClav is at a logic “high”.
Figure 11 presents a timing diagram that illustrates the behavior of various Transmit UTOPIA Interface block
signals, when the Transmit UTOPIA Interface block is operating in the “Cell-Level” Handshaking Mode.
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