XRT73LC00 Datasheet, PDF(41/53 Page) Exar Corporation

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XRT73LC00 Datasheet, PDF (41/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

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PRELIMINARY

XRT73LC00

E3/DS3/STS-1 LINE INTERFACE UNIT

REV. P1.0.1

B. access the Microprocessor Serial Interface and

write a â1â into the RNRZ bit-field in Command

COMMAND REGISTER CR3 (ADDRESS = 0X03)

RNRZ LOSMUT CLK2DIS RCLK2INV RCLK1INV

After these steps are taken, the XRT73LC00 outputs

Single-Rail data to the Receiving Terminal Equipment

via the RPOS and RCLK1 (or RCLK2) output pins as

illustrated in Figure 27 and Figure 28.

NOTE: The RNEG output pin is internally tied to GND

whenever this feature is enabled.

FIGURE 27. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL FORMAT FROM THE

RECEIVE SECTION OF THE XRT73LC00 TO THE RECEIVING TERMINAL EQUIPMENT

Terminal

Equipment

(E3/DS3 or STS-1

Framer)

RxPOS

RPOS

RCLK1, 2 RCLK1, 2

Receive

Logic

Block

Exar E3/DS3/STS-1 LIU

FIGURE 28. THE BEHAVIOR OF THE RPOS AND RCLK1 OUTPUT SIGNALS WHILE THE XRT73LC00 IS TRANSMIT-

TING SINGLE-RAIL DATA TO THE RECEIVING TERMINAL EQUIPMENT

RPOS

RCLK1

4.0 DIAGNOSTIC FEATURES OF THE

XRT73LC00

The XRT73LC00 supports equipment diagnostic ac-

tivities by supporting the following Loop-Back modes

in the chip:

â¢ Analog Local Loop-Back

â¢ Digital Local Loop-Back

â¢ Remote Loop-Back.

4.1 THE ANALOG LOCAL LOOP-BACK MODE

When the XRT73LC00 is configured to operate in the

Analog Local Loop-Back Mode, the XRT73LC00 ig-

nores any signals that are input to the RTIP and

RRING input pins. The Transmitting Terminal Equip-

ment transmits clock and data into the XRT73LC00

via the TPDATA, TNDATA and TCLK input pins. This

data is processed through the Transmit Clock Duty

Cycle Adjust PLL and the HDB3/B3ZS Encoder. Fi-

nally, this data outputs to the line via the TTIP and

TRING output pins and is looped back into the AGC/

Receive Equalizer Block. Consequently, this data is

also processed through the Receive Section of the

XRT73LC00. After this post-loop-back data has been

processed through the Receive Section it outputs to

the Near-End Receiving Terminal Equipment via the

RPOS, RNEG, RCLK1 and RCLK2 output pins.

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