XRT73LC00 Datasheet, PDF (3/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

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PRELIMINARY
XRT73LC00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
FEATURES ................................................................................................................................................ 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1. Block Diagram of the XRT73LC00 .................................................................................................... 1
ORDERING INFORMATION ............................................................................................... 2
Figure 2. Pin Out of the XRT73LC00 in the 44 Pin TQFP ................................................................................ 2
TABLE OF CONTENTS .........................................................................................................I
PIN DESCRIPTION ............................................................................................................. 3
ELECTRICAL CHARACTERISTICS ................................................................................. 11
ABSOLUTE MAXIMUM RATINGS ................................................................................................... 11
DC ELECTRICAL CHARACTERISTICS ............................................................................................................ 11
AC ELECTRICAL CHARACTERISTICS ............................................................................................................ 12
Figure 3. Timing Diagram of the Transmit Terminal Input Interface ............................................................... 13
Figure 4. Timing Diagram of the Receive Terminal Output Interface ............................................................. 13
Figure 5. Transmit Pulse Amplitude Test Circuit for DS3, E3 and STS-1 Rates ............................................ 13
AC ELECTRICAL CHARACTERISTICS (CONT’D) LINE SIDE PARAMETERS ........................................... 16
Figure 6. ITU-T G.703 Transmit Output Pulse Template for E3 Applications ................................................. 17
Figure 7. Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications ............................ 17
Figure 8. Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ........... 18
Figure 9. Microprocessor Serial Interface Data Structure .............................................................................. 18
AC ELECTRICAL CHARACTERISTICS (CONT.) ................................................................................... 19
Figure 10. Timing Diagram for the Microprocessor Serial Interface ............................................................... 19
SYSTEM DESCRIPTION ................................................................................................... 20
THE TRANSMIT SECTION ............................................................................................................................ 20
THE RECEIVE SECTION .............................................................................................................................. 20
THE MICROPROCESSOR SERIAL INTERFACE ................................................................................................ 20
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73LC00 IS OPERATING IN THE HARD-
WARE MODE ...................................................................................................................................... 20
1.0 Selecting the Data Rate ............................................................................................. 21
TABLE 2: SELECTING THE DATA RATE FOR THE XRT73LC00 VIA THE E3 AND STS-1/DS3 INPUT PINS (HARDWARE
MODE) ............................................................................................................................................... 21
COMMAND REGISTER CR4 (ADDRESS = 0X04) ........................................................................................... 21
TABLE 3: SELECTING THE DATA RATE FOR THE XRT73LC00 VIA THE STS-1/DS3 AND THE E3 BIT-FIELDS WITHIN
COMMAND REGISTER CR4 (HOST MODE) .......................................................................................... 21
2.0 The Transmit Section ................................................................................................ 22
2.1 THE TRANSMIT LOGIC BLOCK .............................................................................................................. 22
Figure 11. The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Transmitting Ter-
minal Equipment to the Transmit Section of the XRT73LC00 ...................................................... 22
Figure 12. How the XRT73LC00 Samples the Data on the TPDATA and TNDATA Input Pins ..................... 22
2.1.1 Accepting Single-Rail Data from the Terminal Equipment ................................................. 23
COMMAND REGISTER CR1 (ADDRESS = 0X01) ........................................................................................... 23
Figure 13. The Behavior of the TPDATA and TCLK Input Signals While the Transmit Logic Block is Accepting
Single-Rail Data From the Terminal Equipment ........................................................................... 23
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ...................................................................... 23
2.3 THE HDB3/B3ZS ENCODER BLOCK .................................................................................................... 24
2.3.1 B3ZS Encoding ....................................................................................................................... 24
Figure 14. An Example of B3ZS Encoding ..................................................................................................... 24
2.3.2 HDB3 Encoding ...................................................................................................................... 24
Figure 15. An Example of HDB3 Encoding .................................................................................................... 24
2.3.3 Enabling/Disabling the HDB3/B3ZS Encoder ...................................................................... 25
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY ........................................................................................... 25
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