XRT73LC00 Datasheet, PDF (26/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73LC00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.1
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PRELIMINARY
The manner that the LIU handles Dual-Rail data is
described below and illustrated in Figure 12. The
XRT73LC00 typically samples the data on the TPDA-
TA and TNDATA input pins on the falling edge of
TCLK.
TCLK is typically a clock signal that is of the selected
data rate frequency. For the E3 data rate, TCLK is
34.368 MHz. For the DS3 data rate, TCLK is 44.736
MHz and for the SONET STS-1 rate, TCLK is 51.84
MHz. In general, if the XRT73LC00 samples a “1” on
the TPDATA input pin, the Transmit Section of the de-
vice ultimately generates a positive polarity pulse via
the TTIP and TRING output pins across a 1:1 trans-
former. If the XRT73LC00 samples a “1” on the
TNDATA input pin, the Transmit Section of the device
ultimately generates a negative polarity pulse via the
TTIP and TRING output pins across a 1:1 transform-
er.
2.1.1 Accepting Single-Rail Data from the Ter-
minal Equipment
Do the following if data is to be transmited from the
Terminal Equipment to the XRT73LC00 in Single-Rail
format (a binary data stream) without having to con-
vert it into a Dual-Rail format.
A. Configure the XRT73LC00 to operate in the
HOST Mode or,
B. access the Microprocessor Serial Interface and
write a “1” into the TXBIN (TRANSMIT BINary)
bit-field in Command Register 1.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4
D3
D2
D1
D0
TXOFF
TAOS TXCLKINV TXLEV TXBIN
X
X
X
X
1
After taking these steps, the Transmit Logic Block ac-
cepts Single-Rail data via the TPDATA input pin. The
XRT73LC00 samples this input pin on the falling edge
of the TCLK clock signal and encodes it into the ap-
propriate bipolar line signal across the TTIP and
TRING output pins.
NOTES:
1. In this mode the Transmit Logic Block ignores the
TNDATA input pin.
2. If the Transmit Section of the XRT73LC00 is config-
ured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 13 illustrates the behavior of the TPDATA and
TCLK signals when the Transmit Logic Block has
been configured to accept Single-Rail data from the
Terminal Equipment.
FIGURE 13. THE BEHAVIOR OF THE TPDATA AND TCLK INPUT SIGNALS WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
Data
TPDATA
TCLK
1
1
0
0
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
CUITRY
The on-chip Pulse-Shaping circuitry in the Transmit
Section of the XRT73LC00 has the responsibility for
generating pulses of the shape and width to comply
with the applicable pulse template requirement. The
widths of these output pulses are defined by the width
of the half-period pulses in the TCLK signal.
Allowing the widths of the pulses in the TCLK clock
signal to vary significantly could jeopardize the chip’s
ability to generate Transmit Output pulses of the ap-
propriate width, thereby failing the applicable Pulse
Template Requirement Specification. The chips abili-
ty to generate compliant pulses could depend upon
the duty cycle of the clock signal applied to the TCLK
input pin.
In order to combat this phenomenon, the Transmit
Clock Duty Cycle Adjust circuit was designed into the
XRT73LC00. The Transmit Clock Duty Cycle Adjust
Circuitry is a PLL that was designed to accept clock
pulses via the TCLK input pin at duty cycles ranging
from 30% to 70% and to regenerate these signals
with a 50% duty cycle.
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