XRT81L27 Datasheet, PDF (4/30 Pages) Exar Corporation – SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
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RAOS[6:0] (ADDRESS 0101) ...................................................................................................................... 18
PDTX[6:0] (ADDRESS 0110) ....................................................................................................................... 18
2.0 The transmit section ............................................................................................................................... 19
2.1 THE TRANSMIT LOGIC BLOCK. ............................................................................................................... 19
Figure 7. The Interface for the Transmission of Data From the Transmitting Terminal Equipment
to the Transmit Section of the XRT81L27 ......................................................................... 19
2.1.1 Dual-rail input mode .................................................................................................................. 19
Figure 8. Dual Rail Data from the Terminal .................................................................................... 19
2.1.2 Single-rail input mode ............................................................................................................... 19
Figure 9. Single-Rail Data From the Terminal ............................................................................... 20
2.1.3 TClk input .................................................................................................................................. 20
2.2 THE ENCODER BLOCK ........................................................................................................................... 20
2.2.1 HDB3 Encoding ......................................................................................................................... 20
Figure 10. HDB3 Encoding .............................................................................................................. 20
2.3 THE MUX BLOCK .................................................................................................................................. 20
2.3.1 Timing Control Block ................................................................................................................. 21
2.3.2 The Transmit Clock Duty Cycle Adjust Circuit .......................................................................... 21
2.3.3 Transmit All Ones ...................................................................................................................... 21
2.4 THE PULSE SHAPING CIRCUIT ............................................................................................................... 21
Figure 11. ITU-T G.703 Pulse Template .......................................................................................... 22
2.5 THE LINE DRIVER BLOCK ...................................................................................................................... 22
2.6 INTERFACING THE TRANSMIT SECTIONS OF THE XRT81L27 TO THE LINE ............................................... 22
Figure 12. Illustration of how to interface the Transmit Sections of the XRT81L27 to the Line (for
75 or 120W Applications) ................................................................................................... 23
3.0 The Receive Section ............................................................................................................................... 23
3.1 INTERFACING THE RECEIVE SECTIONS TO THE LINE ............................................................................... 23
Figure 13. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 75W
(Transformer-Coupled) Applications ................................................................................ 24
Figure 14. Schematic for Interfacing the Receive Sections of the XRT81L27 to the Line for 120W
(Transformer-Coupled) Applications ................................................................................ 24
3.2 CAPACITIVE-COUPLING THE RECEIVER TO THE LINE ............................................................................... 25
Figure 15. Capacitive - Coupled Receive Sections of the XRT81L27 to the Line (for Balanced
120W Applications) ............................................................................................................. 25
3.3 THE RECEIVE EQUALIZER BOCK ............................................................................................................ 25
3.4 THE PEAK DETECTOR AND SLICER BLOCK ............................................................................................. 26
3.5 THE LOS DETECTOR BLOCK ................................................................................................................. 26
Figure 16. Package Outline Drawing .............................................................................................. 27
REVISIONS ................................................................................................................................................. 28
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