XRT81L27 Datasheet, PDF (16/30 Pages) Exar Corporation – SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
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Once the CS input pin has been asserted, the type of
operation and the target register address must be
specified. This information is supplied to the MSI by
writing eight serial bits of information into the SDI in-
put. Each of these bits is clocked into the MSI from
the SDI input on the rising edge of SCLK. These eight
bits are identified and described next.
Bit 1 - R/W (Read/Write) Bit
This bit is clocked into the SDI input on the first rising
edge of SCLK after CS has been asserted. This bit
indicates whether the current operation is a Read or
Write operation. A “1” in this bit specifies a Read from
the XRT81L27, a “0” in this bit specifies a Write to the
device.
Bits 2 through 5: The four (4) bit Address Values
(labeled A0, A1, A2 and A3)
The next four rising edges of the SCLK provide the 4-
bit address value for this operation. The address se-
lects the appropriate Command/Control Register in
the XRT81L27. The address bits must be supplied to
the SDI input pin in ascending order with the LSB
(least significant bit) first.
Bits 6 and 7:
The next two bits, (A4 and A5) must be set to “0” as
shown in Figure 6.
Bit 8:
The value of A6 is a “don’t care” but must be clocked.
1.1.2 Data phase of the (MSI) operation
The Microprocessor Serial Interface (MSI) must next
be supplied with 8 additional clocks with the relative
timing of Figure 5. Table 10 provides essential values
for both the selection and data phases of the MSI op-
eration. If the operation specified is a Read, the
XRT81L27 will output data on the SDO pin from the
addressed register. Data is output in ascending order
with the LSB first
If a Write operation has been activated, the external
hardware/Micro must supply the first seven (7) bits to
be written into the selected register. The eighth bit is
a “Don’t care” as only seven bits are used in each of
the registers. These bits are input LSB first.
At the end of the serial shift phase the data is loaded
in parallel into the addressed register. If any register
bit was already set, that bit must be included in the in-
put bit stream. Therefore one must either keep an im-
age of the register status in the micro or do a “read-
modify-write” operation to maintain the state of each
bit that isn’t changing.
FIGURE 5. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
CS
SCLK
SDI
t21
t22
t23
t24
R/W
t27
t25
t26
A0
A1
t29
t28
CS
SCLK
t30
t31
SDO _Hi-Z
D0
D1
Hi-Z
SDI
t33
D2
t32
D7
14