XRT81L27 Datasheet, PDF (18/30 Pages) Exar Corporation – SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY

XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
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1.2 Description of the Command Registers
A listing of these Command Registers, their binary/
hex Addresses and their Bit-Formats are in Table 9.
All bits are reset to zero by activation of the Reset sig-
nal (RST, pin 3). All other registers (0111 through
1111) (0x07 through 0x0F) in the address range are
reserved.
TABLE 9: MICROPROCESSOR REGISTER ADDRESS AND CONTROL
REGISTER
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GLOBAL COMMAND CONTROL REGISTER (READ/WRITE)
0000/0x00 reserved ARAOS
EXLOS
MUTE
SR/DR
CODE
RClkP
TClkP
CHANNEL CONTROL REGISTERS (READ/WRITE)
0001/0x01 reserved
LLB6
LLB5
LLB4
LLB3
LLB2
LLB1
LLB0
0010/0x02 reserved
RLB6
RLB5
RLB4
RLB3
RLB2
RLB1
RLB0
0011/0x03 reserved
ALB6
ALB5
ALB4
ALB3
ALB2
ALB1
ALB0
0100/0x04 reserved TAOS6
TAOS5
TAOS4
TAOS3
TAOS2
TAOS1
TAOS0
0101/0x05 reserved RAOS6
RAOS5
RAOS4
RAOS3
RAOS2
RAOS1
RAOS0
0110/0x06 reserved PDTx6
PDTx5
PDTx4
PDTx3
PDTx2
PDTx1
PDTx0
BIT #
6
5
4
3
2
1
0
TABLE 10: COMMAND CONTROL REGISTER - ADDRESS 0000 - HEX 0X00
(COMMON TO ALL SEVEN CHANNELS)
NAME
FUNCTION
REGISTER TYPE
ARAOS Automatic Receive All Ones:
R/W
Writing a "1" to this bit globally enables receive “all one data” insertion at
RPOS/RNEG upon receive LOS condition.
EXLOS Extended LOS:
R/W
Writing a "1" to this bit extends the number of zeros at the receive input to
4096 bits before LOS is declared.
MUTE Receive Output Muting:
R/W
Writing a "1" to this bit mutes the receive data output at RPOS/RNEG to a
“Low” state upon LOS detection EXCEPT when AROAS is set.
SR/DR Single-rail/Dual-rail:
R/W
Writing a "1" to this bit selects single-rail mode operation.
Writing a "0" to select dual-rail mode operation.
CODE Coding and Decoding:
R/W
In Single-Rail mode ONLY, selects HDB3 encoding and decoding when set.
Under all other conditions, AMI encoding and decoding is selected.
RClkP Receive Clock Polarity:
R/W
Writing a "1" to this bit selects, receive output data to be updated on the rising
edge of RCLK and a "0" to update on the falling edge of RClk.
TClkP Transmit Clock Polarity:
R/W
Writing a "1" to this bit selects, input data to be sampled on the rising edge of
TClk and a "0" to sample on the falling edge of TClk.
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