XR16C2552 Datasheet, PDF (36/36 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO

XR16C2552
REV. 1.0.0
xr
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
4.9 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 22
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................. 23
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 23
4.12 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 24
4.13 ALTERNATE FUNCTION REGISTER (AFR) - READ/WRITE ..................................................................... 24
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 25
ABSOLUTE MAXIMUM RATINGS...................................................................................26
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 26
ELECTRICAL CHARACTERISTICS ................................................................................26
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................26
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................27
TA=-40o to +85oC, Vcc is 2.97 to 5.5V, 70 pF load where applicable ...................................................................... 27
FIGURE 12. CLOCK TIMING............................................................................................................................................................. 28
FIGURE 13. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 28
FIGURE 14. DATA BUS READ TIMING .............................................................................................................................................. 29
FIGURE 15. DATA BUS WRITE TIMING............................................................................................................................................. 29
FIGURE 17. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 30
FIGURE 16. RECEIVE READY AND INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B...................................................... 30
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 31
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 31
FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B............................ 32
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 32
PACKAGE DIMENSIONS (44 PIN PLCC) .......................................................................33
REVISION HISTORY............................................................................................................................. 34
TABLE OF CONTENTS ............................................................................................................ I
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