XR16C2552 Datasheet, PDF (16/36 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO

XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
xr
REV. 1.0.0
.
TABLE 7: INTERNAL REGISTERS DESCRIPTION.
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 IER RD/WR 0
0
0
0 1 0 ISR RD FIFOs FIFOs
0
Enabled Enabled
0 Modem RX Line TX
RX
Stat. Stat. Empty Data
Int.
Int.
Int
Int.
Enable Enable Enable Enable _{LCR[7] = 0}
0
INT INT INT INT
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
0 1 0 FCR WR RXFIFO RXFIFO 0
Trigger Trigger
Bit-1 Bit-0
0
DMA TX
RX FIFOs
Mode FIFO FIFO Enable
Enable Reset Reset
011
LCR RD/WR Divisor Set TX Set Par- Even Parity Stop Word Word
Enable Break
ity
Parity Enable Bits Length Length
Bit-1 Bit-0
1 0 0 MCR RD/WR 0
0
0 Internal OP2# Rsvd RTS# DTR#
Loop- Output _(OP1#) Output Output
back Control
Control Control
Enable
1 0 1 LSR RD RX FIFO THR & THR
RX
RX
RX
RX
RX
Global TSR Empty Break Fram- Parity Over- Data
Error Empty
ing Error run Ready
Error
Error
1 1 0 MSR RD
CD#
Input
RI#
Input
DSR#
Input
CTS# Delta Delta Delta Delta
Input CD# RI# DSR# CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Baud Rate Generator Divisor
0 0 0 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
001
010
DLM RD/WR
AFR RD/WR
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
0
Bit-2 Bit-1 Bit-0
RXRDY# Baudout# Concur-
Select Select rent Write
LCR[7] = 1
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
See “Receiver” on page 12.
4.2 Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 11.
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