XR16C2552 Datasheet, PDF (32/36 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO

XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
xr
REV. 1.0.0
FIGURE 20. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
ISR is read
TX FIFO no
longer empty
Last Data Byte
Transmitted
S D0:D7 T
T_SRT
T_WRI
T_SI
TX FIFO
Empty
T_WT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA#
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Start
Bit
Stop
Bit
S D0:D7 T
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
Last Data Byte
Transmitted
S D0:D7 T
ISR is read
TX FIFO no
T_SRT
longer empty
T_SI
T_WRI
TX FIFO
Full
At least 1
empty location
in FIFO
TX FIFO
Empty
T_WT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA
32