XR16C2552 Datasheet, PDF (3/36 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO

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REV. 1.0.0
XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
NAME
44-PLCC
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
15
I Address data lines [2:0]. These 3 address lines select one of the internal registers in
A1
14
UART channel A/B during a data bus transaction.
A0
10
D7
9
I/O Data bus lines [7:0] (bidirectional).
D6
8
D5
7
D4
6
D3
5
D2
4
D1
3
D0
2
IOR#
24
I Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
IOW#
20
I Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
CS#
18
I UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between
the user CPU and the 2552.
CHSEL
16
I Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a
logic 1 selects UART channel A. Normally, CHSEL could just be an address line from
the user CPU such as A3. Bit-0 of the Alternate Function Register (AFR) can tempo-
rarily override CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially useful during the
initialization routine.
INTA
34
O UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see Figures 16- 21.
INTB
17
TXRDYA#
1
TXRDYB#
32
O UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see Figures 16- 21.
O ^{UART channel A Transmitter Ready (active low). The output provides the TX}
FIFO/THR status for transmit channel A. If it is not used, leave it
unconnected.
O UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B. If it is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
3