XR16C2552 Datasheet, PDF (12/36 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO

XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
xr
REV. 1.0.0
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X
Clock
Transmit Shift Register (TSR)
M
L
S
S
B
B
TXNOFIFO1
2.10.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when the FIFO and the TSR
become empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO MODE
Data Byte
Transmit FIFO
THR
THR Interrupt (ISR bit-1) when TX
FIFO becomes empty. FIFO is
enabled by FCR bit-0=1.
16X Clock
Transmit Data Shift Register
(TSR)
T XF IF O 1
2.11 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit
on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
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