XR16C2552 Datasheet, PDF (13/36 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO

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REV. 1.0.0
XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.11.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift Data Bit
Register (RSR)
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 10. RECEIVER OPERATION IN FIFO MODE
16X Clock
16 bytes by 11-bit
wide FIFO
Receive Data
Byte and Errors
Receive Data Shift Data Bit
Register (RSR)
Validation
Receive Data Characters
RX FIFO
RHR
RHR Interrupt (ISR bit-2) when FIFO fills
up to trigger level.
FIFO is Enabled by FCR bit-0=1
RXFI
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