XR21B1421 Datasheet, PDF (29/50 Pages) Exar Corporation – Enhanced 1-Ch Full-Speed

XR21B1421
Table 8: GPIO Config Bit Positions
Bit
15:14
13
12
11
10
9:8
7
6
5:4
3
2
1
0
GPIO/Pin
9
8
7
6
5
4
3
2
1
0
Pin Name
Reserved
GPIO9/DSR#
GPIO8/DTR#
GPIO7/RI#
GPIO6/CD#
Reserved
GPIO5/RXT
GPIO4/TXT
Reserved
GPIO3/RS485
GPIO2/CTS#
GPIO1/RTS#
GPIO0/CLK
Table 9: Clock Divider High Bit Positions
Bit
7:0 High Period
Description
Table 10: Clock Divider Low Bit Positions
Bit
7:0 Low Period
Description
Output clock frequency is determined by the formula 24 MHz / (High period + Low period) unless both values are 0. For
example, if both Clock Divider High and Clock Divider Low are set to a value of 1, the clock will be 12 MHz with a 50% duty
cycle. If both high and low periods are set to 0 the clock frequency will be 24 MHz. This clock will be selected as an output if
the SET_PIN_CONFIG or the SET_GPIO_CONFIG report selects the clock output.
Output clock must be enabled by GPIO_MODE1 CLK_EN field of this report.
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Rev 1B