XR21B1421 Datasheet, PDF (15/50 Pages) Exar Corporation – Enhanced 1-Ch Full-Speed

XR21B1421
RX FIFO Low Latency
In normal operation, all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to minimize host
processing. When there are 64 bytes of data in the RX FIFO, the XR21B1421 will acknowledge a bulk-in request from the
host and transfer the data packet. If there are less than 64 bytes in the RX FIFO, the XR21B1421 may respond to the bulk-
in request with a NAK indicating that data is not ready to transfer at that time. However, if there are less than 64 bytes in the
RX FIFO and no data has been received for more than 3 character times, the XR21B1421 will acknowledge the bulk-in
request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this behavior may increase latency unacceptably. The low latency
mode is automatically set whenever the baud rate is set to a value of less than 46921 bps. Additionally, a user may manu-
ally enable the low latency mode using the SET_TRANSFER_MODE report (0x48) to immediately transfer any received
data in the RX FIFO to the USB host without waiting for 3 character times.
GPIO
Each UART has 10 GPIO pins in addition to the TX and RX pins. Each GPIO pin may also be configured for one or more
special functions. Please refer to the pin descriptions for the default functionality of each of the general purpose I/Os.
Clock Out
The GPIO0/CLK pin may be configured as a clock output using the SET_PIN_CONFIG or SET_GPIO_CONFIG reports.
The output frequency of the clock out may be programmed between 24 MHz and approximately 47 KHz. The duty cycle
may also be programmed from 50/50 to single low or high going pulse. The default values of 0 for both DIV_HI and DIV_LO
will result in a frequency of 24 MHz. For any non-zero values for DIV_HI and DIV_LO, the clock frequency is determined by
the formula:
FREQ = 24 MHz / (DIV_HI + DIV_LO).
The duty cycle is determined by the ratio of DIV_HI to DIV_LO. GPIO0 will output this clock if is enabled in the GPIO_-
MODE register.
Flow Control
The XR21B1421 is able to perform both hardware and software flow control. Both hardware and software flow control
modes are configured via the SET_UART_CONFIG report. In both modes, flow control is asserted when the bytes in the RX
FIFO reach the watermark set in the RX_THRESHOLD setting. Hardware flow control may either be RTS/CTS or DTR/DSR
controlled. Note that although the default pin configuration for GPIO1/RTS# and GPIO2/CTS# are for RTS output and CTS
input respectively, the hardware RTS/CTS flow control mode must be set in order to utilize the flow control functionality.
Alternately, the pin configurations may be changed to GPIO functionality using the SET_PIN_CONFIG or SET_GPIO_-
CONFIG reports for these pins to be used for GPIO functionality.
Automatic RTS/CTS Hardware Flow Control
Automatic RTS/CTS flow control is used to prevent data overrun errors in the local RX FIFO using the RTS signal to the
remote UART. The RTS signal will be asserted (low) when there are less than 450 bytes in the receive FIFO. When the RX
FIFO reaches the 450 byte threshold, the RTS pin will be deasserted. The CTS# input of the remote UART is monitored to
suspend/restart the transmitter. Refer to Figure 6. Conversely, when the remote UART reaches its receive FIFO threshold,
its RTS will be deasserted, and the XR21B1421 CTS input will cause the device to suspend data transmission.
© 2014 Exar Corporation
15 / 50
exar.com/XR21B1421
Rev 1B