XR21B1421 Datasheet, PDF (14/50 Pages) Exar Corporation – Enhanced 1-Ch Full-Speed

XR21B1421
Normal receive operation with 5, 6, 7 or 8-bit data
Received data is stored in the RX FIFO. Any parity, framing or overrun error or break status information related to the data
is discarded. The receive data format is shown in Figure 4.
7, 8, or 9 bit data
1^ST byte 7 6 5 4 3 2 1 0 _{7 = ‘0’ in 7 bit mode}
Figure 4: Normal Operation Receive Data Format
Normal receive operation with 9-bit data
The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun error or break
status information related to the data is discarded.
Wide mode receive operation with 5, 6, 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received data. The sec-
ond byte consists of the error bits and break status. The wide mode receive data format is shown in Figure 5.
5, 6, 7 or 8 bit mode
1^ST byte 7 6 5 4 3 2 1 0 5, 6, and 7 = ‘0’ in 5, 6, or 7 bit mode
2^ND byte x x x x O F B P
9 bit mode
P = Parity Error (=’0' if not enabled)
B = Break
F = Framing Error
O = Overrun Error
X = ‘0’
1^ST byte 7 6 5 4 3 2 1 0
2^ND byte x x x x O F B 8
B = Break
F = Framing Error
O = Overrun Error
X = ‘0’
Figure 5: Wide Mode Receive Data Format
Wide mode receive operation with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of the received
data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received / checked. The remainder of
the 2nd byte consists of the framing and overrun error bits and break status.
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