XRD98L61_01 Datasheet, PDF (28/38 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L61
CCD Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
Reset Reject
Switches Turn OFF
φ3
Figure 17. Pixel Rate Clock Timing with RSTreject=1
Reset Reject
In the default state, the reset reject switches (φ3) are
always ON, they are not clocked. The reset pulse of
each pixel is transmitted to the first stage of the PGA.
Depending on the PGA gain and the actual voltage
level of the reset pulse, this could cause the first stage
of the PGA to rail. During the Black Level sampling, the
PGA should have enough time to recuperate, but as a
precaution, we have included the Reset Reject option.
When RSTreject = 1, the reset reject switches are
turned OFF at the end of the SPIX pulse, and turned ON
again at the start of the SBLK pulse. This will effec-
tively reject the reset pulse and prevent it from railing
the PGA.
SPIXpol=0, the leading edge is the falling edge and the
trailing edge is the rising edge.
DelayA[2:0] controls the delay added to the leading
edge of SBLK. This positions the falling edge of
internal signal φ1.
DelayA[5:3] controls the delay added to the trailing
edge of SBLK. This positions the rising edge of internal
signal φ1.
DelayB[2:0] controls the delay added to the leading
edge of φ2. This positions the falling edge of internal
signal φ2.
Aperture Delays
One of the most difficult tasks in designing a digital
camera is optimizing the pixel timing for the CCD, CDS
and ADC. We have included the programmable aper-
ture delay function to help simplify this job.
There are two serial interface registers, DelayA &
DelayB, used to program the aperture delays. Each
register is divided into 3 delay parameters. Each delay
parameter is 3 bits wide. Each delay parameter can be
set to add from 0ns to 7ns of delay.
The delays are added to the clock signals after the
polarity control. This means the definition of leading
edge and trailing edge depends on the polarity control
bit for each clock. For the default case, SBLKpol=0 &
DelayB[5:3] controls the delay added to the trailing
edge of SPIX. This positions the rising edge of internal
signal φ2.
DelayB[8:6] is only used when SPIXopt=0. It controls
the delay from the trailing edge of SBLK to the start of
the internal φ2 control. This delay is in addition to
DelayA[5:3], the SBLK trailing edge delay.
DelayA[8:6] controls the delay added to ADCLK. This
is a simple delay. It adds the same delay to both the
rising and falling edges of ADCLK to create φ4.
Rev. 2.00
28