XRD98L61_01 Datasheet, PDF (16/38 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L61
SERIAL INTERFACE READ BACK
The readback function is used to view the content of
the serial interface registers as well as several key
registers in the calibration logic. Readback is enabled
by writing a 1 to the RBenable bit of the Readback
register, bit D9 of register 62.
In the readback mode, the content of the selected
register is output on the 10 MSBs of the ADC output
bus pins DB[11:2]. As long as valid clocks and CCD
signal are applied, the calibration will continue to
function properly during readback (internally the ADC
data is still sent to the calibration logic).
Registers are selected for readback by writing to the
RBreg[8:0] bits in the Readback register, bits D8 to D0
of register 62. If RBreg[8:6]=000, then RBreg[5:0] are
used to address the serial interface registers. Currently
only register addresses 0 to 14, 62 and 63 are defined.
If RBreg[8:6]≠000, then RBreg[5:0] are ignored and
RBreg[8:6] are used to address registers in the calibra-
tion logic. Currently only three calibration registers are
accessible.
RBenable RBreg
8
0
x
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
RBreg
7
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
RBreg
6
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
RBreg
5
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
x
x
Rbreg
4
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
x
x
RBreg
3
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
x
x
x
RBreg
2
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
x
x
x
RBreg
1
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
x
x
x
RBreg
0
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
x
x
x
Selected Register
none (ADC data output)
Gain
Offset
Calibration
Wait A
Wait B
OB Lines
CDAC
FDAC
Control
Polarity
Clock
Delay A
Delay B
DAC0
DAC1
ReadBack
Reset
FDAC output from Cal. logic
CDAC output from Cal. logic
Avg. output from Cal logic
Table 2. Read-back Register Selection
Rev. 2.00
16