XRD98L61_01 Datasheet, PDF (15/38 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L61
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ReadBack RBenable RBreg[8] RBreg[7] RBreg[6] RBreg[5] RBreg[4] RBreg[3] RBreg[2] RBreg[1] RBreg[0]
Default
0
0
0
0
0
0
0
0
0
0
Readback Register (Reg. 62, Address 111110)
The readback register is used to enable the readback
function and select a register for readback.
RBenable=0, Readback disabled.
RBenable=1, Readback enabled. Contents of se-
lected register is output on DB[11:2] pins.
RBreg[8:0], select register to read from, see table in
Serial Interface Read Back section.
Reset
Default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset
0
0
0
0
0
0
0
0
0
0
Reset Register (Reg. 63, Address 111111)
The Reset register is used to reset the entire chip.
Reset=0, Normal operation.
Reset=1, Resets the chip. The Reset bit will auto-
matically reset after approximately 10 ns delay.
Rev. 2.00
15