XRD98L61_01 Datasheet, PDF (10/38 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L61
Address bits
Data bits
Reg. Name
Gain
Offset
Calibration
Wait A
Wait B
OB Lines
CDAC
FDAC
Control
Polarity
Clock
Delay A
Delay B
DAC0
DAC1
A5 A4 A3 A2 A1 A0
000 000
000 001
000 010
000 011
000 100
000 101
000 110
000 111
001 000
001 001
001 010
001 011
001 100
001 101
001 110
D9
PGA[9]
0
Avg[2]
1
WL[11]
0
FDAC[9]
0
DIGtest
0
CLKtest
0
D8 D7 D6
D5 D4
D3
D2
D1
PGA[8] PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1]
0
0
0
0
0
0
0
0
OB[7] OB[6]
OB[5] OB[4] OB[3] OB[2] OB[1]
1
0
0
0
0
0
0
Avg[1] Avg[0] Mode LFrame DNS[1] DNS[0] FastCal Hold
0
1
0
0
1
1
1
0
WL[10] WL[9] WL[8] WL[7] WL[6] WL[5] WL[4] WL[3]
0
0
0
0
0
0
0
0
WL[1]
0
OBL[7] OBL[6] OBL[5] OBL[4] OBL[3] OBL[2] OBL[1]
0
0
0
0
0
0
1
CDAC[8] CDAC[7] CDAC[6] CDAC[5] CDAC[4] CDAC[3] CDAC[2] CDAC[1]
0
0
0
0
0
0
0
0
FDAC[8] FDAC[7] FDAC[6] FDAC[5] FDAC[4] FDAC[3] FDAC[2] FDAC[1]
0
0
0
0
0
0
0
0
ADCtest NoCDS LowPwr
OE DAC1pd DAC0pd AFEpd ADCpd
0
0
0
1
1
1
0
0
SBLKpol SPIXpol CALpol CLAMPpol *Reserved
0
0
0
0
0
Nullamp CMtest Fastclk CLAMPopt OneShot ClampCal SPIXopt RSTreject
0
0
0
0
0
0
0
0
DelayA[8] DelayA[7] DelayA[6] DelayA[5] DelayA[4] DelayA[3] DelayA[2] DelayA[1]
0
0
0
0
0
0
0
0
DelayB[8] DelayB[7] DelayB[6] DelayB[5] DelayB[4] DelayB[3] DelayB[2] DelayB[1]
0
0
0
0
0
0
0
0
DAC0[7] DAC0[6] DAC0[5] DAC0[4] DAC0[3] DAC0[2] DAC0[1]
0
0
0
0
0
0
0
DAC1[7] DAC1[6] DAC1[5] DAC1[4] DAC1[3] DAC1[2] DAC1[1]
0
0
0
0
0
0
0
D0
PGA[0]
0
OB[0]
0
ManCal
0
WL[2]
0
WL[0]
1
OBL[0]
0
CDAC[0]
0
FDAC[0]
0
PwrDwn
0
ADCpol
0
VSreject
0
DelayA[0]
0
DelayB[0]
0
DAC0[0]
0
DAC1[0]
0
ReadBack
Reset
RBenable RBreg[8] RBreg[7] RBreg[6]
111110 0
0
0
0
111 111
RBreg[5] RBreg[4] RBreg[3]
0
0
0
RBreg[2]
0
RBreg[1]
0
RBreg[0]
0
Reset
0
Table 1. Serial Interface Register Address Map & default values
Gain
Default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PGA[9] PGA[8] PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]
0
0
0
0
0
0
0
0
0
0
Gain Register (Reg. 0, Address 000000)
The Gain register is used to set the gain of the Programmable Gain Amplifier (PGA).
Code 0000000000 is minimum gain (0 dB). Codes 1011111111 and greater are maximum gain (36 dB).
See the Programmable Gain Amplifier (PGA) section for more information.
Offset
Default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OB[7] OB[6] OB[5] OB[4] OB[3] OB[2] OB[1] OB[0]
0
0
1
0
0
0
0
0
0
0
Offset Register (Reg. 1, Address 000001)
The Offset register is used to set the target ADC output code for Optical Black pixels.
See the Black Level Offset Calibration section for more information.
NOTE: *Reserved Test register bit. Used for factory test only. Please do not modify.
Rev. 2.00
10