XRD98L61_01 Datasheet, PDF (17/38 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L61
CORRELATED DOUBLE SAMPLE/HOLD (CDS)
The function of the CDS block is to sense the voltage
difference between the black level and video level for
each pixel. The PGA then amplifies this difference to
the desired level for the ADC. The CDS and PGA are
fully differential. The CCDin pin should be connected,
via a capacitor, to the CCD output signal. The REFin
pin should be connected, via a capacitor, to the CCD
“Common” voltage (typically the CCD ground is used
as the “Common” voltage). These capacitors, C1 and
C2, are typically 0.01µF + 10% or better matching.
The timing for the switches shown in Figure 6 are
determined by φ1, φ2, and φ3. φ1, φ2, and φ3 are
internally generated from the timing signals SBLK and
SPIX shown in Figures 17 & 18. φ3 (reset reject
switches) are closed to simplify the operation de-
scribed below.
At the beginning (or end) of every video line, the DC
restore switch forces one side of the external capaci-
tors to an internal bias level (Vbias1=1.2V). The DC
restore switch is controlled by the combination of the
CLAMP input signal ANDed with the φ2 clock.
During the black reference phase of each CCD pixel,
the φ1 (Sample Black Reference) switches are turned
on, shorting the PGA1 inputs to a second bias level
(Vbias2). The Coarse Offset DAC adds an adjustment
to the bias level (Vbias2) to cancel black level offset in
the CCD signal. When the φ1 switches turn off, the
pixel black reference level is sampled on the internal
black sample capacitors, and the PGA is ready to gain
up the CCD video signal.
During the video phase of each CCD pixel, the differ-
ence between the pixel black level and video level is
transmitted through the internal black sample capaci-
tors and converted to a fully differential signal by the
PGA1 amplifier. At this time, the φ2 (Sample Pixel
value) switches turn on, and the internal video sample
capacitors track the amplified difference. The Fine
Offset DAC adds offset adjustment to the PGA2 output
(post gain).
External
DC Blocking
Capacitors
CCD
CCDin
C1
REFin
C2
CDS
Vbias2
PGA
φ1
φ3
Coarse
Offset
φ2
DAC
Internal
Black Sample PGA1
Capacitors
CLAMP
φ2
DC Restore Switches
Vbias1=1.2V
Internal
Video Sample
Capacitors
Fine
Offset
DAC
PGA2
Rev. 2.00
Figure 6. CDS and PGA Block Diagram
17