P0120003P Datasheet, PDF (9/13 Pages) Eudyna Devices Inc – 800mW GaAs Power FET (Pb-Free Type)

P0120003P
800mW GaAs Power FET (Pb-Free Type)
♦Caution: Power Supply Sequence
For safe operation, electric power should be supplied in
following sequence. First, the negative voltage should be
applied on the gate, and the voltage should be more negative
than the pinch-off voltage when you turn on the power
supply. Then, drain bias can be applied. Finally, you can turn
on the RF signal.
When turning off the power supply, the sequence should be
(1)RF signal (2)Drain (3)Gate.
+6V
R1
Q1a
Technical Note
SUMITOMO ELECTRIC
R3 Vds
Q1b
Gat e
0V
Vo lt age
Drain _0V
Vo lt age
On
Bias Voltage
Bias Voltage
On
More Than 1mS
Off
Off
More Than 1mS
♦Bias Circuit
[Passive Biasing]
If you use a fixed bias circuit, you sometimes need to control
the gate bias to get the same Ids, since the devices have some
margin of pinch-off voltage (Vp) variation depending on the
wafer lots. If you employ a fixed Vgs biasing for your
system, you should closely monitor the drain current,
particularly when new wafer lots are introduced.
[Active Biasing]
We recommend using an active bias circuit, which can
eliminate the influence of Vp variation. An example of an
active bias circuit called “current mirror ” is shown below.
Here, two PNP transistors having the minimum variation of
Ibe characteristics are used. These transistors adjust Vgs by
changing Vds automatically. It will realize the constant
current characteristics, regardless of the temperature.
The circuit should be connected directly in line with where
the voltage supplies would be normally connected with the
application circuit. Of course a matching circuit is required,
but it is not shown in this figure.
[Note]
In the measurements of RF performance (Pout vs Pin, etc)
using the application circuit described before, the active bias
circuit herein was not utilized. The application circuits were
biased directly from two power supplies.
R2
GND
R4
R5
Vgs
-5V
P0110003P
P0120003P
Application
Circuit
GND
Vds
+5.9V
Ids
220mA
Q1
UM T1N (Rohm)
R1
16Ω 1/10W
R2
1.8kΩ 1/10W
R3
0.22Ω RL series (SUSUM U)
R4
1kΩ 1/10W
R5
1.3kΩ 1/10W
If you used Ids other than 220mA, you can calculate the
resistance values as follows:
R4 set to be 1kΩ
I₁: Ic of Q1a I₂:Ic of Q1b
V_be1: Vbe of Q1a V_be2: Vbe of Q1b
R1=(+6V-Vds+V_be2-V_be1)/I₁=(+6V-Vds)/I₁
R2=(Vds-V_be2)/I₁
R3=(+6V-Vds)/(Ids+I₂)
R5=|-5V-Vgs|/I₂
♦Attention to Heat Radiation
In the layout design of the printed circuit board (PCB) on
which the power FETs are attached, the heat radiation to
minimize the device junction temperature should be taken
into account, since it significantly affects the MTTF and RF
performance. In any environment, the junction temperature
should be lower than the absolute maximum rating during
the device operation and it is recommended that the thermal
design has enough margin.
Specifications and information are subject to change without notice.
2003-11
Sumitomo Electric Industries, Ltd. 1,Taya-cho, Sakae-ku, Yokohama, 244-8588 Japan
Phone: [phone] Fax: [phone] e-mail : [e-mail] Web Site: www.sei.co.jp/GaAsIC/
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