NUC946ADN Datasheet, PDF (261/376 Pages) List of Unclassifed Manufacturers – 32-BIT ARM926EJ-S BASED MCU

NUC946ADN
32-BIT ARM926EJ-S BASED MCU
Global Interrupt Status Register (FMIISR)
Register
FMIISR
Address
R/W
0xB000_D008 R/W
Description
Global Interrupt Status Register
Reset Value
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
DTA_IF
Bits
[0]
Descriptions
DTA_IF
DMAC READ/WRITE Target Abort Interrupt Flag (Read Only)
This bit indicates DMAC received an ERROR response from internal AHB bus
during DMA read/write operation. When Target Abort is occurred, please
reset all engine.
0 = No bus ERROR response received.
1 = Bus ERROR response received.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
NOTE: No matter interrupt enable is turn on or not, the interrupt flag will be set when target condition is
occurred.
Publication Release Date: July. 26, 2011
261
Revision: A5