NUC946ADN Datasheet, PDF (25/376 Pages) List of Unclassifed Manufacturers – 32-BIT ARM926EJ-S BASED MCU

NUC946ADN
32-BIT ARM926EJ-S BASED MCU
7.2.4 AHB Bus Arbitration
The system bus is AHB-compliant and supports modules with standard AHB master or slave interfaces.
The AHB arbiter has two priority-decision modes, i.e., the fixed priority mode and the rotate priority mode.
In the rotate priority mode, there are three types for AHB-Master bus. The selection of modes and types is
determined on the PRTMOD0 and PRTMOD1bits in the Arbitration Control Register. PRTMOD0 is used to
control the fixed priority of AHB1 (CPU AHB-Lite) Bus and PRTMOD1 is used to control the fixed priority of
AHB2 Master Bus.
7.2.4.1 Fixed Priority Mode
Fixed priority mode is selected if PRTMODx = 0. The order of priorities on the AHB mastership among the
on-chip master modules, listed in Table 7.2.3, is fixed. If two or more master modules request to AHB at
the same time, the mastership is always granted to the module with the highest priority.
Table 7.2.3 AHB Bus Priority Order in Fixed Priority Mode
Priority
Sequence
PRTMOD0 = 0
AHB1 Bus
PRTMOD1 = 0
AHB2 Bus
1 (Lowest)
2
3
4
5
6
7
8
9 (Highest)
ARM CPU Instruction
ARM CPU Data
---
---
---
---
---
---
---
AHB Bridge
---
---
SDIO(FMI)
USB Device
USB Host
EMC Controller
---
The ARM core normally has the lowest priority under the fixed priority mode; however, this chip provides a
mechanism to raise the priority to the highest. If the IPEN bit (bit-1 of Arbitration Control Register) is set
to 1, the IPACT bit (bit-2 of Arbitration Control Register) will be automatically set to 1 while an unmasked
external interrupt occurs. Under this circumstance, the ARM core gains the highest AHB priority.
The programmer can recover the original priority order by directly writing “0” to clear the IPACT bit. For
example, this can be done that at the end of an interrupt service routine. Note that IPACT only can be
automatically set to 1 by an external interrupt when IPEN = 1. It will not take effect if a programmer to
directly write 1 to IPACT to raise ARM core’s AHB priority.
Publication Release Date: July 26, 2011
25
Revision: A5