NUC946ADN Datasheet, PDF (137/376 Pages) List of Unclassifed Manufacturers – 32-BIT ARM926EJ-S BASED MCU

NUC946ADN
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32-BIT ARM926EJ-S BASED MCU
Memory to I/O and I/O to Memory
1. Software must set the [REQ_ATV], [ACK_ATV] and [GDMAMS] bits in GDMA_CTLx register
corresponding to I/O pin with pull high or pull low properly first, and then set the current
GDMA_DADRx to start the I/O to Memory with descriptor fetch transfer.
2. The descriptor lists stop transfer until the RUN bit was zero in descriptor list when external I/O request
triggered once. The RUN bit can be set when external I/O request triggered again under the
NON_DSPTRMODE bit was zero in descriptor list. The trigger period of the external I/O has a timing
limitation whatever the GDMA was in single or burst mode, and the periodic trigger of the external I/O
must be less than 38 MCLK.
3. Each GDMA lists can operate after clearing interrupt status. The descriptor lists stop transfer until the
RUN bit was zero or interrupt status was set.
4. The next Descriptor address, Source Address, Destination Address and Command information must be
set properly in every Descriptor list. Especially, every bit of the Command information will update the
GDMA_CTLx and GDMA_TCNTx registers at every initiation of descriptor list.
NOTE: The [BLOCK] bit of GDMA_CTLx register is disabled when the descriptor mode of the I/O to
memory is enabled.
NOTE: GDMA can change mode with following description:
Descriptor-fetch of each channel can be stopped until the current transfer list done. Software can change
Descriptor mode to Non-Descritpor mode by writing 0x04 to GDMA_DADRx register during the current
descriptor transfer operating.
Non-Descriptor fetch can be stopped until current transfer count finished when software programs the
GDMA_CTLx register with gdmaen bit cleared or softreq cleared.
NOTE: Once software programs the current GDMA_DADRx register, GDMA will fetch the descriptor list
from memory and fill the data to next GDMA_DADRx, current GDMA_SRCBx, current GDMA_DSTBx,
current GDMA_CTLx and current GDMA_TCNTx registers automatically. The fourth word in descriptor list
includes the information for GDMA_CTLx and GDMA_TCNTx registers.
NOTE: The descriptor fetch function only occurs when current GDMA_DADRx [RUN] bit is set and
GDMA_DADRx [NON_DSPTRMODE] is cleared. The current GDMA_DADRx will be updated by next
GDMA_DADRx at every descriptor stops.
7.6.2.2 Ordering function in Descriptor fetch mode
This function determines the source of next descriptor address. If [ORDEN] is set, the GDMA controller
fetches the next descriptor from current GDMA_DADRx [Descriptor Address] + 16 bytes.
If this bit is cleared, GDMA fetches the next descriptor from the current GDMA_DADRx [Descriptor
Address].
GDMA_DADRx [ORDEN] is only relevant to descriptor-fetch function (GDMA_DADRx [NON_DSPTRMODE]
= 0).
Publication Release Date: July. 26, 2011
137
Revision: A5