82C862 Datasheet, PDF (11/51 Pages) List of Unclassifed Manufacturers – FireLink USB Dual Controller Quad Port USB

PAR
FRAME#
IRDY#
TRDY#
STOP#
FireLink USB
82C862
76
O
Even Parity: The 82C862 calculates PAR for both the address and data phases
of PCI cycles. PAR is valid one PCI clock after the associated address or data
phase, but may or may not be valid for subsequent clocks. It is calculated based
on 36 bits - AD[31:0] plus C/BE[3:0]#. "Even" parity means that the sum of the 36
bit values plus PAR is always an even number, even if one or more bits of
C/BE[3:0]# indicate invalid data.
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I/O Cycle Frame: This signal is driven by the current PCI bus master to indicate the
(s/t/s) beginning and duration of an access. The master asserts FRAME# at the
beginning of a bus cycle, sustains the assertion during data transfers, and then
negates FRAME# in the final data phase.
FRAME# is an input when the 82C862 is the target and an output when it is the
initiator.
FRAME# is tristated from the leading edge of RESET# and remains tristated until
driven as either a master or slave by the 82C862.
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I/O Initiator Ready: IRDY#, along with TRDY#, indicates whether the 82C862 is able
(s/t/s) to complete the current data phase of the cycle. IRDY# and TRDY# are both
asserted when a data phase is completed.
During a write, the 82C862 asserts IRDY# to indicate that it has valid data on
AD[31:0]. During a read, the 82C862 asserts IRDY# to indicate that it is prepared
to accept data.
IRDY# is an input when the 82C862 is a target and an output when it is the
initiator.
IRDY# is tristated from the leading edge of RESET# and remains tristated until
driven as either a master or a slave by the 82C862.
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I/O Target Ready: TRDY#, along with IRDY#, indicates whether the 82C862 is able
(s/t/s) to complete the current data phase of the cycle. TRDY# and IRDY# are both
asserted when a data phase is completed.
When the 82C862 is acting as the target during read and write cycles, it performs
in the following manner:
1. During a read, the 82C862 asserts TRDY# to indicate that it has placed valid
data on AD[31:0].
2. During a write, the 82C862 asserts TRDY# to indicate that is prepared to
accept data.
TRDY# is an input when the 82C862 is the initiator and an output when it is the
target.
TRDY# is tristated from the leading edge of RESET# and remains so until driven
as either a master or a slave by the 82C862.
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I/O Stop: STOP# is an output when the 82C862 is the target and an input when it is
(s/t/s) the initiator. As the target, the 82C862 asserts STOP# to request that the master
stop the current cycle. As the master, the assertion of STOP# by a target forces
the 82C862 to stop the current cycle.
STOP# is tristated from the leading edge of RESET# and remains so until driven
by the 82C862 acting as a slave.
912-2000-030
Revision 1.0
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