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VS1033 Datasheet, PDF (61/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC | |||
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VLSI
Solution y
VS1033a PRELIMINARY
VS1033A
10. VS1033 REGISTERS
10.11.6 Interrupts and Operation
Transmitter operates as follows: After an 8-bit word is written to the transmit data register it will be
transmitted instantly if the transmitter is not busy transmitting the previous byte. When the transmission
begins a TX INTR interrupt will be sent. Status bit [1] informs the transmitter data register empty (or
full state) and bit [0] informs the transmitter (shift register) empty state. A new word must not be written
to transmitter data register if it is not empty (bit [1] = â0â). The transmitter data register will be empty
as soon as it is shifted to transmitter and the transmission is begun. It is safe to write a new word to
transmitter data register every time a transmit interrupt is generated.
Receiver operates as follows: It samples the RX signal line and if it detects a high to low transition, a
start bit is found. After this it samples each 8 bit at the middle of the bit time (using a constant timer),
and ï¬lls the receiver (shift register) LSB ï¬rst. Finally the data in the receiver is moved to the reveive
data register, the stop bit state is checked (logic high = ok, logic low = framing error) for status bit[4],
the RX INTR interrupt is sent, status bit[2] (receive data register full) is set, and status bit[2] old state is
copied to bit[3] (receive data overrun). After that the receiver returns to idle state to wait for a new start
bit. Status bit[2] is zeroed when the receiver data register is read.
RS232 communication speed is set using two clock dividers. The base clock is the processor master
clock. Bits 15-8 in these registers are for ï¬rst divider and bits 7-0 for second divider. RX sample
frequency is the clock frequency that is input for the second divider.
Version 0.6, 2005-01-05
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