VS1033 Datasheet, PDF (58/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
10. VS1033 REGISTERS
10.10 Watchdog v1.0 2002-08-26
The watchdog consist of a watchdog counter and some logic. After reset, the watchdog is inactive.
The counter reload value can be set by writing to WDOG CONFIG. The watchdog is activated by writ-
ing 0x4ea9 to register WDOG RESET. Every time this is done, the watchdog counter is reset. Every
65536’th clock cycle the counter is decremented by one. If the counter underflows, it will activate vs-
dsp’s internal reset sequence.
Thus, after the first 0x4ea9 write to WDOG RESET, subsequent writes to the same register with the
same value must be made no less than every 65536×WDOG CONFIG clock cycles.
Once started, the watchdog cannot be turned off. Also, a write to WDOG CONFIG doesn’t change the
counter reload value.
After watchdog has been activated, any read/write operation from/to WDOG CONFIG or WDOG DUMMY
will invalidate the next write operation to WDOG RESET. This will prevent runaway loops from re-
setting the counter, even if they do happen to write the correct number. Writing a wrong value to
WDOG RESET will also invalidate the next write to WDOG RESET.
Reads from watchdog registers return undefined values.
10.10.1 Registers
Reg
0xC020
0xC021
0xC022
Watchdog, prefix WDOG
Type Reset Abbrev
Description
w
0 CONFIG Configuration
w
0 RESET
Clock configuration
w
0 DUMMY[-] Dummy register
Version 0.6, 2005-01-05
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