VS1033 Datasheet, PDF (59/70 Pages) List of Unclassifed Manufacturers – MP3/AAC/WMA/MIDI AUDIO CODEC

VLSI
Solution ^y
VS1033a PRELIMINARY
VS1033A
10. VS1033 REGISTERS
10.11 UART v1.1 2004-10-09
RS232 UART implements a serial interface using rs232 standard.
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Figure 15: RS232 Serial Interface Protocol
When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission begins
with a start bit (logic zero) and continues with data bits (LSB first) and ends up with a stop bit (logic
high). 10 bits are sent for each 8-bit byte frame.
10.11.1 Registers
Reg
0xC028
0xC029
0xC02A
0xC02B
UART registers, prefix UARTx
Type Reset Abbrev
Description
r
0 STATUS[4:0] Status
r/w
0 DATA[7:0] Data
r/w
0 DATAH[15:8] Data High
r/w
0 DIV
Divider
10.11.2 Status UARTx STATUS
A read from the status register returns the transmitter and receiver states.
Name
UART ST FRAMEERR
UART ST RXORUN
UART ST RXFULL
UART ST TXFULL
UART ST TXRUNNING
UARTx STATUS Bits
Bits Description
4 Framing error (stop bit was 0)
3 Receiver overrun
2 Receiver data register full
1 Transmitter data register full
0 Transmitter running
UART ST FRAMEERR is set if the stop bit of the received byte was 0.
UART ST RXORUN is set if a received byte overwrites unread data when it is transferred from the
receiver shift register to the data register, otherwise it is cleared.
UART ST RXFULL is set if there is unread data in the data register.
UART ST TXFULL is set if a write to the data register is not allowed (data register full).
UART ST TXRUNNING is set if the transmitter shift register is in operation.
Version 0.6, 2005-01-05
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